Dynamic buffer allocation in an ATM switch

Efficient and fair use of buffer space in an Asynchronous Transfer Mode (ATM) switch is essential to gain high throughput and low cell loss performance from the network. In this paper a shared buffer architecture associated with threshold-based virtual partition among output ports is proposed. Thresholds are updated based on traffic characteristics on each outgoing link, so as to adapt to traffic loads. The system behavior under varying traffic patterns is investigated via simulation; cell loss rate is the quality of service (QoS) measure used in this study. Our study shows that the threshold based dynamic buffer allocation scheme ensures a fair share of the buffer space even under bursty loading conditions.     

Performance improvement of dynamic buffered ATM switch

Performance of ATM networks depends on switch performance and architecture. This paper presents a simulation study of a new dynamic allocation of input buffer space in ATM switching elements. The switching elements are composed of input and output buffers which are used to store received and forwarded cells, respectively. Efficient and fair use of buffer space in an ATM switch is essential to gain high throughput and low cell loss performance from the network. In this paper, input buffer space of each switching element is allocated dynamically as a function of traffic load. A shared buffer pool is provided with threshold-based virtual partition among input ports, which supplies the necessary input buffer space as required by each input port. The system behaviour under varying traffic loads has investigated using a simulation program. Also, a comparison with a static allocation scheme shows that the threshold based dynamic buffer allocation scheme ensures an increased network throughput and a fair share of the buffer space even under bursty loading conditions.     

Trends in highly scalable crossbar-based packet switch architecture

A combined input and crosspoint queued (CICQ) switch is receiving significant attention to be the next generation high speed packet switch for its scalability; however, a multi-cabinet implementation of a combined input and crosspoint queued (CICQ) switch unavoidably introduces a large round-trip time (RTT) latency between the line cards and switch fabric, resulting a large crosspoint (CP) buffer requirement. In this paper, virtual crosspoint queues (VCQs) that significantly reduces the CP buffer requirement of the CICQ switch is investigated. The VCQs unit resides inside the switch fabric, is dynamically shared among virtual output queues (VOQ) from the same source port, and is operated at the line rate, making the implementation practical. A threshold-based exhaustive round-robin (T-ERR) arbitration is employed to reduce buffer hogging at VCQ. The T-ERR at VCQ and CP arbiters serves packets residing in a longer queue more frequently than packet residing in a shorter queue. Consequently, the T-ERR, drastically increases the throughput of the CICQ switch with small CP buffers. A multi-cabinet implementation of CICQ switch do not support multicasting traffic well since a combination of small CP buffer in the switch fabric and a large RTT latency between the line cards and switch fabric results in non-work conservation of the intra-switch link. Deployment of multicast FIFO buffer between the input buffer and CP buffer shows a promise. With its ability to achieve high throughput independent of RTT and switch port size, the integration of the VCQ architecture and T-ERR scheduler to the CICQ switch is ideal for supporting ever-increasing Internet traffic that requires higher data rate, larger switch size, and efficient multicasting.     

How to reduce packet dropping in a bufferless NoC

Networks on‐chip (NoCs) interconnect the components located inside a chip. In multicore chips, NoCs have a strong impact on the overall system performance. NoC bandwidth is limited by the critical path delay. Recent works show that the critical path delay is heavily affected by switch port buffer size. Therefore, by removing buffers, switch clock frequency can be increased. Recently, a new switching technique for NoCs called Blind Packet Switching (BPS) has been proposed, which is based on removing the switch port buffers. Since buffers consume a high percentage of switch power and area, BPS not only improves performance but also reduces power and area. In BPS, as there are no buffers at the switch ports, packets cannot be stopped and stored on them. If contention arises packets are dropped and later reinjected, negatively affecting performance. In order to prevent packet dropping, some techniques based on resource replication have been proposed. In this paper, we propose some alternative and complementary techniques that do not rely on resource replication. By using them, packet dropping is highly reduced. In particular, packet dropping is completely removed for a very wide network traffic range. Moreover, network throughput is increased and packet latency is reduced. Copyright © 2010 John Wiley & Sons, Ltd.     

Modelling a packet-switching network

The basic traffic parameters involved in the analysis of a packet-switching network and its nodes are identified. The paper considers a virtual call of the CCITT X.25 protocol to derive the basic flow in a network. Traffic offered to the various hierarchical levels of the network depends on the information increase imposed by the protocol. Several efficiency levels are derived at different time levels, and are used to relate network traffic to user traffic. The sensitivities of these packet levels to packet size, packet delay and window size are evaluated for both interactive and batch traffic.     

Improved Competitive Guarantees for QoS Buffering

We consider a network providing Differentiated Services (DiffServ), which allow Internet Service Providers (ISPs) to offer different levels of Quality of Service (QoS) to different traffic streams. We study two types of buffering policies that are used in network switches supporting QoS. In the FIFO type, packets must be transmitted in the order they arrive. In the uniform bounded delay type, there is a maximal delay time associated with the switch and each packet must be transmitted within this time, or otherwise it is dropped. In both models the buffer space is limited, and packets are lost when the buffer overflows. Each packet has an intrinsic value, and the goal is to maximize the total value of transmitted packets. Our main contribution is an algorithm for the FIFO model with arbitrary packet values that for the first time achieves a competitive ratio better than 2, namely 2-ε for a constant ε gt; 0. We also describe an algorithm for the uniform bounded delay model which simulates our algorithm for the FIFO model, and show that it achieves the same competitive ratio.     

基于标签的POF网络虚拟化技术研究

针对SDN新一代转发控制分离技术——协议无感知转发(POF),提出了协议字段全开放的SDN网络虚拟化架构。该架构提出了基于标签的网络虚拟化技术和POF物理交换机流表分配技术,通过网络虚拟化中间件将POF交换机与POF控制器之间传递的消息进行转换,对物理网络中传输的数据进行标签封装,从而区分不同网络切片与虚拟链路的流量信息。与已有的虚拟化中间件Flow Visor、Open Virtex、Co Visor等相比,该虚拟化中间件全面支持POF协议,通过物理网络中的数据的标签化处理,实现了SDN转发平面全字段开放的网络虚拟化。同时,基于该套架构,实现了POF网络虚拟化中间件系统POFHyper Visor,并验证了该POF网络虚拟化中间件系统的功能与性能,经测试,虚拟化消息处理能力损失在17.1%~29.9%。     

On the defense of the distributed denial of service attacks: anon-off feedback control approach

Proposes a coordinated defense scheme of distributed denial of service (DDoS) network attacks, based on the backward-propagation, on-off control strategy. When a DDoS attack is in effect, a high concentration of malicious packet streams are routed to the victim in a short time, making it a hot spot. A similar problem has been observed in multiprocessor systems, where a hot spot is formed when a large number of processors access simultaneously shared variables in the same memory module. Despite the similar terminologies used here, solutions for multiprocessor hot spot problems cannot be applied to that in the Internet, because the hot traffic in DDoS may only represent a small fraction of the Internet traffic, and the attack strategies on the Internet are far more sophisticated than that in the multiprocessor systems. The performance impact on the hot spot is related to the total hot packet rate that can be tolerated by the victim. We present a backward pressure propagation, feedback control scheme to defend DDoS attacks. We use a generic network model to analyze the dynamics of network traffic, and develop the algorithms for rate-based and queue-length-based feedback control. We show a simple design to implement our control scheme on a practical switch queue architecture     

Providing per-session deterministic quality of service guarantees in cross-path packet switch

Recently, a quasi-static routing scheme called path switching was proposed for large-scale packet switch systems. The path-switched Clos network is called a cross-path switch. Cross-path switch is capable of supporting multirate and multicast traffic. In this paper, we develop a general framework for it to handle multimedia traffic. We obtain upper bounds on the delay and backlog at the cross-path switch on a per-session basis, wherein no packet lost or delay bound violation is allowed. Our results show that these bounds much depend on the way of token assignment at the central stage. To understand such dependence, we quantify the effect of the token assignment on the switch performance. From these results, we design an effective token assignment scheme to achieve better performance guarantees in the switch. We show that cross-path switch with such token assignments always provides near-optimal performance guarantees to each data session.     

Switching modules for ATM switching systems and their interconnection networks

In this paper, we investigate the performance of a nonblocking packet switch having input buffers and a limited amount of buffers within the switch fabric, where contention for the output ports occurs. A novel scheduling scheme based on head of line blocking is proposed, which improves the performance significantly. For uniform random traffic, a 16 × 16 switch has an achievable throughput equal to 87.5%. We also studied the performance of the switch modules under unbalanced and bursty traffic. Examination of the switch under two delay-priority classes reveals that the achievable throughput can be increased to 91%. To build a large size switching system, a three-stage interconnection network is used, which meets the demands of large scale ATM switch design, such as (1) modularity, (2) relaxed synchronization, (3) guaranteed high performance (i.e. high throughput, low variability of delay) without requiring large internal speed-up, and (4) maintaining packet sequence integrity.     

Competitive On-Line Switching Policies

Consider the following problem. A switch connecting n input channels to a single output channel must deliver all incoming messages through this channel. Messages are composed of packets , and in each time slot the switch can deliver a single packet from one of the input queues to the output channel. In order to prevent packet loss, a buffer is maintained for each input channel. The goal of a switching policy is to minimize the maximum buffer size. The setting is on-line; decisions must be made based on the current state without knowledge of future events. This general scenario models multiplexing tasks in various systems such as communication networks, cable modem systems, and traffic control. Traditionally, researchers analyzed the performance of a given policy assuming some distribution on the arrival rates of messages at the input queues, or assuming that the service rate is at least the aggregate of all the input rates. We use competitive analysis, avoiding any prior assumptions on the input. We show O(log n )-competitive switching policies for the problem and demonstrate matching lower bounds.     

Implementing multidestination worms in switch-based parallelsystems: architectural alternatives and their impact

Multidestination message passing has been proposed as an attractive mechanism for efficiently implementing multicast and other collective operations on direct networks. However, applying this mechanism to switch-based parallel systems is nontrivial. In this paper, we propose alternative switch architectures with differing buffer organizations to implement multidestination worms on switch-based parallel systems. First, we discuss issues related to such implementation (deadlock-freedom, replication mechanisms, header encoding, and routing). Next, we demonstrate how an existing central-buffer-based switch architecture supporting unicast message passing can be enhanced to accommodate multidestination message passing. Similarly, implementing multidestination worms on an input-buffer-based switch architecture is discussed, and two architectural alternatives are presented that reduce the wiring complexity in a practical switch implementation. The central-buffer-based and input-buffer-based implementations are evaluated against each other, as well as against the corresponding software-based schemes. Simulation experiments under a range of traffic (multiple multicast, bimodal, varying degree of multicast, and message length) and system size are used for evaluation. The study demonstrates the superiority of the central-buffer-based switch architecture. It also indicates that under bimodal traffic the central-buffer-based hardware multicast implementation affects background unicast traffic less adversely compared to a software-based multicast implementation. These results show that multidestination message passing can be applied easily and effectively to switch-based parallel systems to deliver good multicast and collective communication performance     

自相似流量下包丢失的尺度特性

IP网络上的设备故障与流量拥塞经常导致网络数据丢包现象,研究网络上丢包行为的特性对于拥塞控制机制的设计、网络性能分析和服务质量保证都具有重要意义。文章基于ON/OF模型构造了具有长相关性包到达过程的链路流量,研究了在单路复用网络模型上的丢包特性,分析了丢包过程中体现的长相关特性,以及流量长相关性、缓冲区大小、输出链路速率因素与其长相关特性的关系。     

Performance of a beacon enabled IEEE 802.15.4 cluster with downlink and uplink traffic

The performance of an IEEE 802.15.4 compliant network operating in the beacon enabled mode with both downlink and uplink traffic is analyzed through discrete time Markov chains and the theory of M/G/1 queues. The model considers acknowledged transmissions and includes the impact of different network and traffic parameters such as the packet arrival rate, packet size, inactive period between the beacons, and the number of stations. We investigate the nonsaturation region and outline the conditions under which the network abruptly goes to saturation. The analysis of stability of the network queues shows that the stability of the downlink queue at the coordinator is the most critical for network operation. Due to the abruptness with which the switch from nonsaturation to saturation occurs, the network operating point has to be carefully chosen according to the volume of downlink traffic. Furthermore, our model shows that certain features prescribed by the standard actually limit the performance of 802.15.4 networks.     

无尺度网络的数据包传输元胞自动机模型研究*

为了更真实地模拟网络行为,提出了一种基于无尺度网络的数据包传输元胞自动机模型,模型中通过增加缓存队列大小和提高中心节点的处理速度来减少丢包数,提高网络性能。仿真结果表明,在元胞交互规则的作用下,数据包发送速率,缓存队列大小和丢包数在时间序列上都具有自相似特性,自相似程度呈现负相关;它们在时间序列上是长程相关的,在功率谱图中都具有幂律分布特性,在高频段呈现出白噪声特性。     

基于SDN的数据中心动态优先级多路径调度算法

随着云计算技术和分布式业务的发展,数据中心内部“东西向”大象流量激增,这部分大象流在调度不当的情况下容易发生碰撞,造成链路拥塞。本文提出一种基于软件定义网络（SDN）的动态优先级多路径调度算法（DPMS）。该算法根据数据中心流量的特点制定大象流和老鼠流调度模型,充分利用各网络节点间的冗余链路,提高资源利用率;并结合组表优化SDN架构中控制器和交换机的通信模式,降低了数据包处理时延。实验结果表明,相比ECMP和Hedera这2种调度策略,DPMS提高了网络吞吐量和链路利用率,减少了平均流完成时间,网络的整体性能有所提高。     

Port partitioning and dynamic queueing for IP forwarding

With the increase of internet protocol (IP) packets the performance of routers became an important issue in internet/working. In this paper we examine the matching algorithm in gigabit router which has input queue with virtual output queueing. Dynamic queue scheduling is also proposed to reduce the packet delay and packet loss probability. Port partitioning is employed to reduce the computational burden of the scheduler in a switch which matches the input and output ports for fast packet switching. Each port is divided into two groups such that the matching algorithm is implemented within each pair of groups in parallel. The matching is performed by exchanging the pair of groups at every time slot. Two algorithms, maximal weight matching by port partitioning (MPP) and modified maximal weight matching by port partitioning (MMPP) are presented. In dynamic queue scheduling, a popup decision rule for each delay critical packet is made to reduce both the delay of the delay critical packet and the loss probability of loss critical packet. Computational results show that MMPP has the lowest delay and requires the least buffer size. The throughput is illustrated to be linear to the packet arrival rate, which can be achieved under highly efficient matching algorithm. The dynamic queue scheduling is illustrated to be highly effective when the occupancy of the input buffer is relatively high.Scope and purposeTo cope with the increasing internet traffic, it is necessary to improve the performance of routers. To accelerate the switching from input ports to output in the router partitioning of ports and dynamic queueing are proposed. Input and output ports are partitioned into two groups A/B and a/b, respectively. The matching for the packet switching is performed between group pairs (A, a) and (B, b) in parallel at one time slot and (A, b) and (B, a) at the next time slot. Dynamic queueing is proposed at each input port to reduce the packet delay and packet loss probability by employing the popup decision rule and applying it to each delay critical packet.The partitioning of ports is illustrated to be highly effective in view of delay, required buffer size and throughput. The dynamic queueing also demonstrates good performance when the traffic volume is high.     

Competitive On-Line Switching Policies

Abstract. Consider the following problem. A switch connecting n input channels to a single output channel must deliver all incoming messages through this channel. Messages are composed of packets , and in each time slot the switch can deliver a single packet from one of the input queues to the output channel. In order to prevent packet loss, a buffer is maintained for each input channel. The goal of a switching policy is to minimize the maximum buffer size. The setting is on-line; decisions must be made based on the current state without knowledge of future events. This general scenario models multiplexing tasks in various systems such as communication networks, cable modem systems, and traffic control. Traditionally, researchers analyzed the performance of a given policy assuming some distribution on the arrival rates of messages at the input queues, or assuming that the service rate is at least the aggregate of all the input rates. We use competitive analysis, avoiding any prior assumptions on the input. We show O(log n )-competitive switching policies for the problem and demonstrate matching lower bounds.     

High-performance implementation of in-network traffic pacing for small-buffer networks

Demands on data communication networks continue to drive the need for increasingly faster link speeds. Optical packet switching networks promise to provide data rates that are sufficiently high to satisfy the needs of the future Internet core network. However, a key technological problem with optical packet switching is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the widely used Transmission Control Protocol (TCP), do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic at edge networks to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. We have also shown that this traffic pacing can improve the performance of conventional networks that use small buffers (e.g., to reduce the cost of buffer memory on routers). A key challenge in this context is to develop systems that can perform such packet pacing efficiently and at high data rates. In this paper, we present the design and prototype of a hardware implementation of our packet pacing technique. We discuss and evaluate design trade-offs and present performance results from an prototype implementation based on a NetFPGA fieldprogrammable gate array system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe that traffic pacing can be deployed widely to improve the operation of current and future networks.     

A neural-network packet switch controller: scalability, performance, and network optimization

We examine a novel combination of architecture and algorithm for a packet switch controller that incorporates an experimentally implemented optically interconnected neural network. The network performs scheduling decisions based on incoming packet requests and priorities. We show how and why, by means of simulation, the move from a continuous to a discrete algorithm has improved both network performance and scalability. The system's limitations are examined and conclusions drawn as to its maximum scalability and throughput based on today's technologies.