A study on surface grinding of 300 mm silicon wafers

Most of today's IC chips are made from 200 mm or 150 mm silicon wafers. It is estimated that the transition from 200 mm to 300 mm wafers will bring a die cost saving of 30–40%. To meet their customers' needs, silicon wafer manufacturers are actively searching for cost-effective ways to manufacture 300 mm wafers with high quality. This paper presents the results of a study on surface grinding of 300 mm silicon wafers. In this study, a three-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feedrate). The process outputs studied include spindle motor current, surface roughness, grinding marks and depth of subsurface cracks.     

Fine grinding of silicon wafers: a mathematical model for grinding marks

The majority of today’s integrated circuits are constructed on silicon wafers. Fine-grinding process has great potential to improve wafer quality at a low cost. Three papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third paper developed a mathematical model for the chuck shape, addressing one of the technical barriers that have hindered the widespread application of this technology: difficulty and uncertainty in chuck preparation. As a follow up, this paper addresses another technical barrier: lack of understanding on grinding marks. A mathematical model to predict the locus of the grinding lines and the distance between two adjacent grinding lines is first developed. With the developed model, the relationships between grinding marks and various process parameters (wheel rotational speed, chuck rotational speed, and wheel diameter) are then discussed. Finally, results of pilot experiments to verify the model are discussed.     

Fine grinding of silicon wafers: designed experiments

Silicon wafers are the most widely used substrates for semiconductors. The falling price of silicon wafers has created tremendous pressure to develop cost-effective processes to manufacture silicon wafers. Fine grinding possesses great potential to reduce the overall cost for manufacturing silicon wafers. The uniqueness and the special requirements of fine grinding have been discussed in a paper published earlier in this journal. As a follow-up, this paper presents the results of a designed experimental investigation into fine grinding of silicon wafers. In this investigation, a three-variable two-level full factorial design is employed to reveal the main effects as well as the interaction effects of three process parameters (wheel rotational speed, chuck rotational speed and feed-rate). The process outputs studied include grinding force, spindle motor current, cycle time, surface roughness and grinding marks.     

Fine grinding of silicon wafers: effects of chuck shape on grinding marks

Silicon wafers are used for production of most microchips. Various processes are needed to transfer a silicon ingot into wafers. With continuing shrinkage of feature sizes of microchips, more stringent requirement is imposed on wafer flatness. Fine grinding of silicon wafers is a patented technology to produce super flat wafers at a low cost. Six papers on fine grinding were previously published in this journal. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented the mathematical models for the chuck shape and the grinding marks, respectively. The fifth paper developed a mathematical model for the wafer shape and the sixth paper studied machine configurations for spindle angle adjustments. This paper is a follow up of the above-mentioned work. A mathematical model to predict the depth of grinding marks for any chuck shape will be first developed. With the developed model, effects of the chuck shape (as well as the wheel radius) on the depth of grinding marks will be studied. Finally, results of pilot experiments to verify the model will be discussed.     

大尺寸硅片自旋转磨削运动分析及仿真

本文利用数学矩阵方法,建立大尺寸硅片自旋转磨削运动的理论模型,研究了砂轮半径、硅片和砂轮旋转速度、旋转方向等因素的选择及各因素对磨削轨迹的影响,同时还研究了磨粒合成运动速度的变化规律。研究结果表明,随着砂轮半径的增大,磨削轨迹的曲率减小,选用较小直径砂轮将更有利硅片表面质量的提高。当转速比i大于零,随着i值的增大,磨削轨迹的曲率逐渐减小。在转速比i小于零的情形,当转速比i=-2时,磨削轨迹曲率为0,磨削轨迹的形状接近一条直线。磨粒合成运动速度随砂轮转速和硅片转速的增大而增大。     

An experimental study of flat fixed abrasive grinding of silicon wafers using resin-bonded diamond pellets

The purpose of this paper is to investigate the effect of the diamond grain size, the wheel rotation speed, the table rotation speed, and the applied pressure in the vertical flat grinding on the surface roughness of silicon wafers using Taguchi orthogonal array design. Besides, the pits and resistivity on the wafers were studied as well. The experiment results showed that the diamond grain size and the wheel rotation speed of the vertical flat grinding for the roughness of wafers obtained are the relatively larger significant contribution. When the smaller diamond grit size, the faster wheel rotation speed, the faster table rotation speed, and the smaller applied pressure in the flat grinding are employed, the traces produced by the grains are denser and the chip thickness and the depth of cut were smaller, which cause the silicon wafer to produce the higher degree of the ductile grinding. This will lead the wafer surface to produce the smaller amount and size of the pits, thereby generating the lower surface roughness. In addition, the center site of the wafer obtained is the smaller amount and size of the pits than the outer of the wafer, which produces the better surface roughness and the lower resistivity.     

硅片自旋转磨削中基于作用力的微观接触仿真研究

采用杯型金刚石砂轮进行硅片自旋转磨削是典型的硅片超精密磨削加工形式。本试验从其磨削过程中抽象出砂轮微单元与硅片的微观接触作为研究对象,建立基于作用力的仿真模型,采用软件LS-DYNA对自旋转磨削微观作用过程进行了模拟,对作用过程中硅片与砂轮微单元的应力应变情况进行了有限元分析。结果表明:硅片材料存在相应弹性转塑性和塑性转脆性的临界位移与载荷;在硅片塑性区域切向滑动时可在硅片表面产生塑性沟槽与隆起;砂轮微单元上的磨损可依据其仿真数据作出判断。研究为硅片磨削及砂轮磨损机理研究提供支撑。      

Fine grinding of silicon wafers

Silicon wafers are used for the production of most microchips. Various processes are needed to transfer a silicon crystal ingot into wafers. As one of such processes, surface grinding of silicon wafers has attracted attention among various investigators and a limited number of articles can be found in the literature. However, no published articles are available regarding fine grinding of silicon wafers. In this paper, the uniqueness and the special requirements of the silicon wafer fine grinding process are introduced first. Then some experimental results on the fine grinding of silicon wafers are presented and discussed. Tests on different grinding wheels demonstrate the importance of choosing the correct wheel and an illustration of the proper selection of process parameters is included. Also discussed are the effects of the nozzle position and the flow rate of the grinding coolant.     

Simultaneous double side grinding of silicon wafers: a literature review

Silicon wafers are the most widely used substrates for fabricating integrated circuits (ICs). The quality of ICs depends directly on the quality of silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Simultaneous double side grinding (SDSG) is one of the processes to flatten the wire-sawn wafers. This paper reviews the literature on SDSG of silicon wafers, covering the history, machine development (including machine configuration, drive and support systems, and control system), and process modeling (including grinding marks and wafer shape). It also discusses some possible topics for future research.     

Waviness removal in grinding of wire-sawn silicon wafers: 3D finite element analysis with designed experiments

Silicon wafers are used to fabricate more than 90% of integrated circuits. Surface grinding has been used to flatten wire-sawn silicon wafers. A major issue in grinding of wire-sawn wafers is that conventional grinding cannot effectively remove the waviness induced by wire-sawing process. Soft-pad grinding is a promising method to effectively remove waviness. This paper presents the results of three-dimensional (3D) finite element analysis of soft-pad grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal main effects as well as interaction effects of four factors (Young’s modulus, Poisson’s ratio, and thickness of the soft pad, and waviness wavelength of the wafer) on the effectiveness of waviness reduction. Implications of this study to manufacturing are also discussed.     

Microstructure studies of the grinding damage in monocrystalline silicon wafers

1. Introduction The monocrystalline silicon wafer, as an impor-tant substrate of the integrated circuit, is widely used in IC manufacturing. Various processes are needed to transfer a silicon crystal ingot into wafers. Silicon crystallizes in the diamond lattice, with covalent bonding, ensuring an extremely stable spatial ar-rangement of the Si atoms in the monocrystal. It is a brittle material. Most processes can induce me-chanical damage. The depth and nature of the sub-surface damage will…     

造孔剂含量对树脂结合剂硅片减薄砂轮磨削性能的影响

为改善硅片背面减薄效果,在树脂结合剂硅片减薄砂轮里添加造孔剂。通过体积密度测试、扫描电镜观察和磨削实验,研究造孔剂含量对树脂结合剂砂轮结构和磨削性能的影响。结果表明:随着造孔剂体积分数增加、投料比降低,砂轮内部孔隙率增大;且磨削实验证明造孔剂可以提高硅片的表面质量。当造孔剂添加体积分数在10%、体积密度投料比控制在75%时,树脂结合剂硅片减薄砂轮在磨削过程中具有较好的综合磨削性能,磨削出来的硅片表面粗糙度R_a、R_z、R_y值波动范围小,与其他条件下的砂轮磨削的硅片相比,表面一致性好。      

Residual stress analysis on silicon wafer surface layers induced by ultra-precision grinding

Grinding residual stresses of silicon wafers affect the performance of IC circuits. Based on the wafer rotation ultra-precision grinding ma-chine, the residual stress distribution along grinding marks and ground surface layer depth of the ground wafers are investigated using Raman microspectroscopy. The results show that the ground wafer surfaces mainly present compressive stress. The vicinity of pile-ups between two grinding marks presents higher a compressive stress. The stress value of the rough ground wafer is the least because the material is removed by the brittle fracture mode. The stress of the semi-fine ground wafer is the largest because the wafer surface presents stronger phase trans-formations and elastic-plastic deformation. The stress of the fine ground wafer is between the above two. The strained layer depths for the rough, semi-fine, and fine ground wafers are about 7.6 m, 2.6 m, and 1.1 m, respectively. The main reasons for generation of residual stresses are phase transformations and elastic-plastic deformation.     

Finite element analysis for grinding of wire-sawn silicon wafers: a designed experiment

Silicon is the primary semiconductor material used to fabricate microchips. The quality of microchips depends directly on the quality of starting silicon wafers. A series of processes are required to manufacture high quality silicon wafers. Surface grinding is one of the processes used to flatten the wire-sawn wafers. A major issue in grinding of wire-sawn wafers is the reduction and elimination of wire-sawing induced waviness. This paper presents the results of a finite element analysis for grinding of wire-sawn silicon wafers. In this investigation, a four-factor two-level full factorial design is employed to reveal the main effects as well as the interaction effects of four factors (wafer thickness, waviness wavelength, waviness height and grinding force) on effectiveness of waviness reduction. The implications of this study to manufacturing are also discussed.     

金刚石砂轮磨削单晶硅片面形变化规律

磨削减薄过程中,硅片表面产生亚表面损伤,其中的残余应力使硅片产生翘曲变形。因此,研究无光磨磨削时的硅片面形变化规律以评价其加工质量。使用金刚石砂轮无光磨磨削厚度400μm和450μm的硅片并测量其面形。将硅片面形数据从中心向边缘沿径向分割成5个环带,分别研究其面形拟合弯曲曲率半径变化。结果显示:从中心区域到边缘区域,硅片的变形量增大,说明无光磨硅片上的残余应力变大,即磨削加工损伤增大。同时,研究还发现晶向对硅片变形有显著影响,〈110〉晶向区变形与〈100〉晶向区变形差异明显。      

Fine grinding of silicon wafers: a mathematical model for the wafer shape

Over 90% of semiconductors are built on silicon wafers. The fine grinding process has great potential to produce very flat wafers at a low cost. Four papers on fine grinding have been previously published by the authors. The first paper discussed its uniqueness and special requirements. The second one presented the results of a designed experimental investigation. The third and fourth papers presented mathematical models for the chuck shape and the grinding marks, respectively. As a follow up, this paper develops a mathematical model for the wafer shape. After the model is described, its practical applications in wafer manufacturing are discussed.     

cBN砂轮在低速磨削中的应用

cBN砂轮在高速设备上使用非常广泛,但在老式低速磨床上采用cBN砂轮的非常少。我们在这方面做了大胆的尝试,就是在老式磨床上不做任何改进,直接更换相同直径的陶瓷cBN砂轮,通过更换皮带轮改变传动比,把砂轮速度从51.4 m/s提升到64.8 m/s,增大冷却液流量、压力,确定冷却液冲刷位置,改变切削的进给量,使cBN砂轮的一个修整频次内寿命大幅提升。最后证明陶瓷cBN砂轮在低速磨床中一样可以替代刚玉砂轮,并且不需要大的改造投资,可以获得非常好的综合经济效益。     

用磨粒叶序排布砂轮磨削外圆生成的凹坑表面仿真

结构化凹坑表面能够有效降低零件表面的流体拖曳摩擦阻力,从而改善零件在流体中的运动性能。从生物学的叶序排布理论出发,设计了磨粒叶序排布的超硬材料砂轮,并应用该砂轮磨削外圆生成结构化的凹坑表面。利用Matlab软件对磨粒叶序排布砂轮的磨削过程进行运动学仿真,获得了磨粒叶序排布参数及磨削参数对磨削区域内结构化凹坑表面形貌的影响规律。仿真及实验结果表明:转速比影响凹坑的周向排布和凹坑尺寸,转速比越高,凹坑周向排布越密集,凹坑尺寸越小;叶序系数影响凹坑的轴向排布,叶序系数越小,凹坑轴向排布越密集;磨削深度影响凹坑尺寸,磨削深度越深,凹坑宽度和深度越大,毛刺隆起高度越高,约为磨削深度的一半。      

Grinding wheels for manufacturing of silicon wafers: A literature review

Grinding is an important process for manufacturing of silicon wafers. The demand for silicon wafers with better quality and lower price presents tremendous challenges for the grinding wheels used in the silicon wafer industry. The stringent requirements for these grinding wheels include low damage on ground surfaces, self-dressing ability, consistent performance, long wheel lives, and low prices. This paper presents a literature review on grinding wheels for manufacturing of silicon wafers. It discusses recent development in abrasives, bond materials, porosity formation, and geometry design of the grinding wheels to meet the stringent requirements.     

A grinding-based manufacturing method for silicon wafers: generation mechanisms of central dimples on ground wafers

Silicon wafers are the fundamental building blocks for most integrated circuits. The lapping-based manufacturing method currently used to manufacture the majority of silicon wafers will not be able to meet the ever-increasing demand for flatter wafers and lower prices. A grinding-based manufacturing method has been investigated experimentally to demonstrate its potential to manufacture flat silicon wafers at a lower cost. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. This paper, as a follow up, addresses one of the reasons for the poor flatness at the wafer center: central dimples on ground wafers. A finite element model is developed to illustrate the generation mechanisms of central dimples. Then, effects of influencing factors (including Young's modulus and Poisson's ratio of the grinding wheel segment, dimensions of the wheel segment, grinding force, and chuck shape) on the central dimple sizes are studied. Pilot experimental results will be presented to substantiate the predicted results from the finite element model. This provides practical guidance to eliminate or reduce central dimples on ground wafers.