Investigation on X-ray irradiation on nanoscale nitride based charge trapping flash memory devices

Charge trapping flash memory devices are susceptible to charge loss mechanisms induced by high energy irradiation such as thermal neutrons, X-rays, and gamma ray. The loss of trapped charges due to charge loss mechanism has resulted in the degradation in data retention performance and unwanted read failures in field applications. In this work, charge loss mechanisms of nanoscale nitride based charge trapping flash memory devices due to irradiation of high energy X-rays were carefully studied and examined. Nitride based charge trapping flash memory device stored charges in the nitride storage layer of an Oxide-Nitride-Oxide stack. Threshold voltage of the nitride based charge trapping flash memory cells were collected before and after X-ray irradiation done onto the memory devices. Threshold voltage distributions have shown that significant number of cells at the lower end of the program distribution had perturbed from the overall distribution that was caused by X-ray irradiation induced charge loss mechanism. In this study, the effect of the use of 300 μm Zn filter and its proximity to the device under study to mitigate the X-ray irradiation induced charge loss was also thoroughly elucidated. The results have demonstrated that 300 μm Zn filter has significantly improved the immunity of nitride based charge trap flash memory device up to 6.446 times. However, the proximity of the Zn filter to the flash memory device exacerbated up to 7.4280 times due to the impact of secondary effect in X-ray fluorescence to the device under study. Hence, this investigation concluded that X-ray irradiation is a genuine reliability concern for nanoscale nitride based charge trapping flash memory devices. Furthermore, it is recommended to place Zn filter close to X-ray source to significantly mitigate the Vt distribution drift induced by X-ray irradiation.     

Charge retention improvement of charge-trapping type flash device by plasma immersion ion implantation

Electrical characteristics of charge trapping-type flash devices with HfAlO charge trapping layer nitrided by plasma immersion ion implantation (PIII) technique with different implantation energies and time are studied. Utilizing Fowler–Nordheim (FN) operation, the programming speed of flash memory with charge trapping layer nitrided at low implantation energy is faster than that of control sample. The erasing speed of PIII-treated sample is slightly slower than that of control one, which might be due to the formation of silicon nitride in the tunneling oxide. The retention characteristics of all PIII-treated samples are significantly improved. Different peak locations of implanted nitrogen concentrations are formed by different implantation energies, which cause various electrical characteristics of flash devices.     

Erase voltage impact on 0.18μm triple self-aligned split-gate flash memory endurance

The erase voltage impact on the 0.18μm triple self-aligned split-gate flash endurance is studied.An optimized erase voltage is necessary in order to achieve the best endurance.A lower erase voltage can cause more cell current degradation by increasing its sensitivity to the floating gate voltage drop,which is induced by tunnel oxide charge trapping during program/erase cycling.A higher erase voltage also aggravates the endurance degradation by introducing select gate oxide charge trapping.A progressive erase voltage method is proposed and demonstrated to better balance the two degradation mechanisms and thus further improve endurance performance.     

Determination of trapped oxide charge in flash EPROMs and MOSFETswith thin oxides

A technique for determining the sign and the effective density of the trapped oxide charge near the junction transition region, based on the measurement of the gate-induced drain leakage (GIDL) current, is used to investigate the hot-carrier effects resulting from the erase operation and bit-line stress in flash EPROM devices. While the trapped oxide charge depends on the stress conditions, it has been found that a significant amount of hole trapping is likely when a sufficiently large potential difference exists between the gate and junction for either an abrupt or graded junction     

Characterization of the triple-gate flash memory endurance degradation mechanism

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash mem-ory have been detected and analyzed using a tYV erasure method. Different from the commonly degradation phe-nomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in horn-shaped SuperFlash(R) does not occur in the triple-gate flash cell. This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash(R) cell. Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.     

三栅 SuperFlash闪存的耐久性退化机理特性

Write/erase degradation after endurance cycling due to electron trapping events in triple-gate flash memory have been detected and analyzed using a UV erasure method. Different from the commonly degradation phenomenon, write-induced electron trapping in the floating gate oxide, electron trapping in tunneling oxide is observed in triple-gate flash memory. Further, the degradation due to single-electron locally trapping/de-trapping in hornshaped SuperFlash does not occur in the triple-gate flash cell This is because of planar poly-to-poly erasing in the triple-gate flash cell instead of tip erasing in the horn-shaped SuperFlash cell Moreover, by TCAD simulation, the trap location is identified and the magnitude of its density is quantified roughly.     

Gate oxide thickness dependence of edge charge trapping in NMOS transistors caused by charge injection under constant-current stress

This brief reports a study of charge injection-induced edge charge trapping in the gate oxide overlapping the drain extension which has an impact on the drain leakage current. The edge charge trapping is determined for the gate oxide thickness of 6.5, 3.9, and 2.0 nm by using a simple approach to analyze the change of the band-to-band tunneling current measured with a three-terminal gate-controlled-diode configuration. The edge charge trapping has a strong dependence on the gate oxide thickness, and it is different from the charge trapping in the oxide over the channel. A plausible explanation for both the oxide thickness dependence of the edge charge trapping and the difference between the edge charge trapping and the charge trapping over the channel is presented.     

热载流子应力下超薄栅pMOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了4nm pMOSFET的热载流子应力下氧化层陷阱电荷的产生行为.首先,对于不同沟道长度下的热载流子退化,通过直接的实验证据,发现空穴陷阱俘获特性与应力时间呈对数关系.然后对不同应力电压、不同沟道长度下氧化层陷阱电荷(包括空穴和电子陷阱俘获)的产生做了进一步的分析.发现对于pMOSFET的热载流子退化,氧化层陷阱电荷产生分两步过程:在较短的应力初期,电子陷阱俘获是主要机制;而随着应力时间增加,空穴陷阱俘获作用逐渐显著,最后主导了氧化层陷阱电荷的产生.     

热载流子应力下超薄栅p MOS器件氧化层陷阱电荷的表征

利用电荷泵技术研究了 4nmpMOSFET的热载流子应力下氧化层陷阱电荷的产生行为 .首先 ,对于不同沟道长度下的热载流子退化 ,通过直接的实验证据 ,发现空穴陷阱俘获特性与应力时间呈对数关系 .然后对不同应力电压、不同沟道长度下氧化层陷阱电荷 (包括空穴和电子陷阱俘获 )的产生做了进一步的分析 .发现对于 pMOSFET的热载流子退化 ,氧化层陷阱电荷产生分两步过程 :在较短的应力初期 ,电子陷阱俘获是主要机制 ;而随着应力时间增加 ,空穴陷阱俘获作用逐渐显著 ,最后主导了氧化层陷阱电荷的产生.     

Novel SONOS – type nonvolatile memory device with stacked tunneling and charge trapping layers

Operation properties of polysilicon–oxide–nitride–oxide–silicon (SONOS)-type nonvolatile semiconductor memory (NVM) devices with stacked tunneling and charge trapping layers were investigated in this work. Clear enhancement on operation speed and satisfactory retention of NVM device were achieved by adopting stacked tunneling oxide. Enhancement on programming speed but degradation on erasing operation was observed for device with stacked charge trapping layer. Finally, operating characteristics of devices with stacked tunneling oxide, stacked charge trapping layer, and combining both stacked tunneling oxide and charge trapping layer were compared and discussed.     

The nature of charge trapping responsible for thin-oxide breakdown under a dynamic field stress

The trapping of positive and negative charges in silicon dioxide was studied as a function of injection current density and pulse width during dynamic high-field/high-current stress. Trapping of negative charges in oxide under dynamic stress conditions was found to give an accumulated charge to breakdown (Qbd) that was independent of stressing current density if the total injected charge per pulse was kept constant. However, the trapping of positive charges increased significantly as current density was increased. Under dynamic stress with fixed current density, the trapping of negative charge in the oxide increased with increasing pulse width while the trapping of positive charge was independent of pulse width. The experimental data for dynamically stressed devices suggest a strong correlation between the breakdown of thin oxides and the amount of negative charge trapped in them.     

Optimization of hafnium oxide for use in nanoparticle memories

In this work we investigate the dielectric properties of hafnium oxide deposited by RF magnetron sputtering with the purpose to implement it as control oxide for non-volatile memories based on metallic nanoparticles as charge storage centers. The influence of deposition temperature, ambient and post-deposition annealing onto the trapping properties of hafnium oxide, deposited over a tunneling silicon oxide layer, will be discussed and optimized conditions under which no charge trapping is observed into the dielectric stack will be presented.     

A two-dimensional numerical simulation of oxide charge buildup inMOS transistors due to radiation

The authors have developed a time-dependent two-dimensional simulator in order to simulate charge trapping in silicon dioxide due to radiation. The Poisson and continuity equations are solved both in the oxide and the semiconductor. In addition, in order to simulate charge trapping, trap rate equations using first-order trapping kinetics are solved in the oxide. This paper contains the numerical methods used in the simulation and results obtained using this simulator. One of the main results of this simulation is the presence of a lateral variation in the radiation-induced oxide charge in an MOS transistor irradiated with a drain bias     

Degradations due to hole trapping in flash memory cells

Degradation in the hot-electron programmability of the flash memory cell is observed after erasing from the drain. Trapped holes in the oxide near the drain junction are found to be responsible for this degradation. Hole trapping in the oxide also causes another problem known as gate disturb, which is the undesired increase in the threshold voltage of an erased cell during programming of the other cells on the same word line. Threshold-voltage shifts due to gate disturb are used to monitor the amount of trapped holes in the oxide after cell erasure. It is determined that the trapped holes are mainly externally injected from the junction depletion region rather than directly generated in the oxide by the Fowler-Nordheim (F-N) tunneling process     

Charge transport and trapping characteristics in thin nitride-oxidestacked films

A charge transport and trapping model for thin nitride-oxide stacked films between silicon substrates and polysilicon gates is proposed. Nitride-oxide stacked films can be thought of as an oxide film with electron trapping at the nitride/oxide interface. The density of electron trapping is determined by the current-continuity requirement. The electron trapping reduces the leakage current and helps to lower the incidence of early failures for nitride-oxide stacked films     

An investigation of erase-mode dependent hole trapping in flashEEPROM memory cell

Hot-hole generation during electrical erase in flash memory cells was investigated and found to be strongly dependent on the lateral electric field of the gated diode junction. It is shown, by erasing the memory cell at a low source voltage in combination with a negative gate voltage, that the operating point can be chosen well away from the onset of avalanche. Using this erasing scheme appreciably reduces the amount of hole trapping in the tunnel oxide. As a result, data retention is significantly improved as compared with conventional erasure     

Bake induced charge gain in NOR flash cells

Charge gain, caused by localized defects in the tunnel oxide of floating gate devices, is one of the central reliability concerns of flash memory. In this work, we show that charge motion in the poly sidewall spacers of flash cells can also result in substantial charge gain, for nonoptimized processes. Data showing the time, temperature, and field dependencies of this charge gain mechanism are presented. It is shown that the threshold voltage shift caused by charge motion in the poly sidewall spacers follows the simple factorial expression: ΔV _th=C·V_fg·t^α ·e^-ϵ(a)kT/     

Enhanced electron trapping near channel edges in NMOS transistors

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. The edge trapping effect could increase the electrical channel length by as much as 0.5 μm and is independent of the channel length. Possible reasons for the observed phenomena are discussed     

A new technique for hot carrier reliability evaluations of flashmemory cell after long-term program/erase cycles

In this paper, we provide a methodology to evaluate the hot-carrier-induced reliability of flash memory cells after long-term program/erase cycles. First, the gated-diode measurement technique has been employed for determining the lateral distributions of interface state (N_it) and oxide trap charges (Q_ox) under both channel-hot electron (CHE) programming bias and source-side erase-bias stress conditions. A gate current model was then developed by including both the effects of N_it and Q_ox. Degradation of flash memory cell after P/E cycles due to the above oxide damage was studied by monitoring the gate current. For the cells during programming, the oxide damage near the drain will result in a programming time delay and we found that the interface state generation is the dominant mechanism. Furthermore, for the cells after long-term erase using source-side FN erase, the oxide trap charge will dominate the cell performance such as read disturb. In order to reduce the read-disturb, source bias should be kept as low as possible since the larger the applied source erasing bias, the worse the device reliability becomes     

Nitrogen doped multilayer photo catalytically reduced graphene oxide floating gate: Al/PMMA/NrGO/SiO2/p–Si/Au based hybrid gate stack for non volatile memory applications

Photo catalytically assisted, multi–layer nitrogen doped reduced graphene oxide (ML–NrGO) is investigated as a promising charge storage layer in Al/PMMA/NrGO/SiO₂/p–Si/Au structure. A considerable memory window (ΔW) of ∼3.3 V at ± 7 V sweep voltage and long data retention upto ∼ 10⁵ s is demonstrated as an encouraging candidature for emerging memory hierarchies. The clockwise hysteresis supports the hole charge trapping mechanism in the NrGO based structure. The ML–NrGO memory devices provide the rapid programming, saturation of the program transients, store more data at less cost and reduced ballistic transport in the plane perpendicular to NrGO. The facile, solution processable, cost effective device processing and stable retention of the fabricated ML–NrGO based Al/PMMA/NrGO/SiO₂/p–Si/Au flash memory structures proves to be a potential alternative for existing EEPROM based embedded applications and also for commercial scale production of flash memory based on flexible organic electronics.