Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

A framework for assessing amorphous oxide semiconductor thin‐film transistor passivation

Amorphous oxide semiconductor thin‐film transistors (TFTs) are moving towards commercialization for a variety of display applications. Invariably, display applications require a bottom‐gate TFT configuration in which passivation of the top channel layer surface is required. The objective of this work is to propose a conceptual model framework for assessing TFT passivation schemes, within the context of amorphous oxide semiconductor electronics. This model involves first estimating the energy of the charge neutrality levels (CNLs) for the channel and passivation layers. Then, an energy band diagram is drawn to establish the relative position of these CNLs prior to their establishment of intimate contact. A situation in which the passivation layer CNL is below that of the channel layer CNL is considered undesirable because interface state electronic transfer from the channel to the passivation layer leads to formation of an accumulation layer at this interface. Although the opposite case in which the passivation layer CNL is above that of the channel layer CNL is more desirable, the ideal situation would be when both CNLs align because no interface state electronic transfer would occur. This framework is then employed in a discussion of the passivation of indium gallium zinc oxide and zinc tin oxide bottom‐gate TFTs.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Effect on electrical performance of titanium co‐sputtered IZO active‐channel thin‐film transistor

We investigated the electrical performance of Ti–IZO active‐channel layer thin‐film transistors (TFTs) using a radio frequency (RF) magnetron co‐sputtering system to co‐sputter IZO and Ti targets. The samples were fabricated by changing the RF gun power of the IZO. The other parameters such as the RF gun power of the Ti target, oxygen partial pressure [O₂/(Ar + O₂)], and initial and process pressure of the chamber were unchanged. Unlike the sample sputtered only with IZO, the thin films of the Ti–IZO samples could control the oxygen vacancy because Ti reacts with the oxygen in the IZO. Therefore, Ti–IZO thin films can suppress the carrier concentration and thus have an effect on the electrical performance of TFTs.     

Dual‐plate OLED display (DOD) based on amorphous‐silicon (a‐Si) TFT backplane

Abstract— An improved AMOLED with an a‐Si TFT backplane based on a unique structure is reported. The new structure is refered to as a dual‐plate OLED display (DOD). While a top‐emission OLED array is directly fabricated on a TFT backplane, the DOD consists of an upper OLED substrate and a lower TFT substrate, which are independently fabricated. Because the OLED substrate, which is fabricated through the process flow of bottom emission, is attached to the TFT substrate, the light is emitted in the opposite direction to the TFT backplane. The DOD enables the design of large‐sized TFTs and a complicated pixel circuit. It can also not only achieve higher uniformity in luminance in large‐sized displays due to the low electrical resistance of the common electrode, but also wider viewing angles.     

Negative bias illumination stress assessment of indium gallium zinc oxide thin‐film transistors

Electrical performance stability of indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) is evaluated under negative bias illumination stress (NBIS). A bottom‐gate IGZO TFT whose top surface is passivated with zinc tin silicon oxide (ZTSO) exhibits a dramatic improvement in NBIS stability compared with that of an unpassivated, bottom‐gate IGZO TFT. Oxygen chemisorption/desorption at the channel layer top surface is proposed to explain why an unpassivated TFT exhibits significantly more NBIS than a passivated TFT.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Development of 8‐in. oxide‐TFT‐driven flexible AMOLED display using high‐performance red phosphorescent OLED

An 8‐in. flexible active‐matrix organic light‐emitting diode (AMOLED) display driven by oxide thin‐film transistors (TFTs) has been developed. In‐Ga‐Zn‐O (IGZO)‐TFTs used as driving devices were fabricated directly on a plastic film at a low temperature below 200 °C. To form a SiO_x layer for use as the gate insulator of the TFTs, direct current pulse sputtering was used for the deposition at a low temperature. The fabricated TFT shows a good transfer characteristic and enough carrier mobility to drive OLED displays with Video Graphic Array pixels. A solution‐processable photo‐sensitive polymer was also used as a passivation layer of the TFTs. Furthermore, a high‐performance phosphorescent OLED was developed as a red‐light‐emitting device. Both lower power consumption and longer lifetime were achieved in the OLED, which used an efficient energy transfer from the host material to the guest material in the emission layer. By assembling these technologies, a flexible AMOLED display was fabricated on the plastic film. We obtained a clear and uniform moving color image on the display.     

Amorphous‐silicon thin‐film transistors made at 280°C on clear‐plastic substrates by interfacial stress engineering

Abstract— A process temperature of ～300°C produces amorphous‐silicon (a‐Si) thin‐film transistors (TFTs) with the best performance and long‐term stability. Clear organic polymers (plastics) are the most versatile substrate materials for flexible displays. However, clear plastics with a glass‐transition temperature (T_g) in excess of 300°C can have coefficients of thermal expansion (CTE) much larger than that of the silicon nitride (SiN^x) and a‐Si in TFTs deposited by plasma‐enhanced chemical vapor deposition (PECVD). The difference in the CTE that may lead to cracking of the device films can limit the process temperature to well below that of the T_g of the plastic. A model of the mechanical interaction of the TFT stack and the plastic substrate, which provides design guidelines for avoid cracking during TFT fabrication, is presented. The fracture point is determined by a critical interfacial stress. The model was used to successfully fabricate a‐Si TFTs on novel clear‐plastic substrates with a maximum process temperature of up to 280°C. The TFTs made at high temperatures have higher mobility, lower leakage current, and higher stability than TFTs made on conventional low‐T_g clear‐plastic substrates.     

Suspension‐deposited carbon‐nanotube networks for flexible active‐matrix displays

Abstract— The unique properties of carbon nanotubes (CNTs) promise innovative solutions for a variety of display applications. The CNTs can be deposited from suspension. These simple and low‐cost techniques will replace time‐consuming and costly vacuum processes and can be applied to large‐area glass and flexible substrates. Single‐walled carbon nanotubes (SWNTs) have been used as conducting and transparent layers, replacing the brittle ITO, and as the semiconducting layer in thin‐film transistors (TFTs). There is no need for alignment because a CNT network is used instead of single CNTs. Both processes can be applied to glass and to flexible plastic substrates. The transparent and conductive nanotube layers can be produced with a sheet resistance of 400 Ω/□ at 80% transmittance. Such layers have been used to produce directly addressed liquid‐crystal displays and organic light‐emitting diodes (OLED). The CNT‐TFTs reach on/off ratios of more than 10⁵ and effective charge‐carrier mobilities of 1 cm²/V‐sec and above.     

High‐mobility self‐aligned top‐gate oxide TFT for high‐resolution AM‐OLED

High‐mobility and highly reliable self‐aligned top‐gate oxide thin‐film transistor (TFTs) were developed using the aluminum reaction method. Al diffusion to the oxide semiconductor and homogenization of the oxygen concentration in the depth direction after annealing were confirmed by laser‐assisted atom probe tomography. The high mobility of the top‐gate TFT with amorphous indium tin zinc oxide channel was demonstrated to be 32 cm²/V s. A 9.9‐in. diagonal qHD active‐matrix organic light‐emitting diode (AM‐OLED) display was fabricated using a five‐mask backplane process to demonstrate an applicable solution for large‐sized and high‐resolution AM‐OLEDs.     

Microcrystalline silicon: An emerging material for stable thin‐film transistors

Abstract— Top‐gate and bottom‐gate microcrystalline‐silicon thin‐film transistors (TFTs) have been produced at low temperature (150–250°C) by the standard radio‐frequency glow‐discharge technique using three preparation methods: the hydrogen dilution of silane in hydrogen, the layer‐by‐layer technique, and the use of SiF₄‐Ar‐H₂ feedstock. In all cases, a stable top‐gate TFT with mobility values around 1 cm²/V‐sec have been achieved, making them suitable for basic circuit on glass applications. Moreover, the use of SiF₄ gas combined with specific plasma treatments of the a‐SiN:H dielectric produces large columns, even at the interface with the dielectric. This leads to stable bottom‐gate TFTs, fully compatible with today's a‐Si:H production facilities, reaching mobility values up to 3 cm²/V‐sec. These devices are an interesting alternative to laser‐crystallized polysilicon thin films in a growing number of applications.     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Layer‐by‐layer nitrogenation of microcrystalline silicon for TFT applications

Abstract— We have optimized the low‐temperature growth of microcrystalline silicon at 80°C. This material has been used to fabricate bottom‐gate μc‐Si:H TFTs by using a layer‐by‐layer nitrogenation process. By using this process, the amorphous incubation layer can be converted into silicon nitride and leads to an increase in a field‐effect mobility of the TFT.     

Large‐area spatial atomic layer deposition of amorphous oxide semiconductors at atmospheric pressure

Indium gallium zinc oxide (IGZO) is deposited using plasma‐enhanced spatial atomic layer deposition (sALD) on substrates as large as 32 × 35 cm². Excellent uniformity and thickness control leads to high‐performing and stable coplanar top‐gate self‐aligned (SA) thin‐film transistors (TFTs). The integration of a sALD‐deposited aluminum oxide buffer layer into the TFT stack further improves uniformity and stability. The results demonstrate the viability of atmospheric sALD as a novel deposition technique for the flat‐panel display industry.     

Thin‐film transistor mobility limits considerations

The mobility limiting scattering mechanisms for amorphous semiconductors and polar polycrystalline semiconductors are studied in the context of developing new high‐performance thin‐film transistor (TFT) channel layer materials for large‐area electronics. A physics‐based model for carrier transport in an amorphous semiconductor is developed to estimate the mobility limits of amorphous semiconductor TFTs. The model involves band tail state trapping of a diffusive mobility. Simulation reveals a strong dependence on the band tail density of states. This consideration makes it difficult to realize a high‐performance p‐type oxide TFT. A polar crystalline semiconductor may offer a higher mobility but is fundamentally limited by polar optical phonon scattering. Any crystalline TFT channel layer for practical large‐area applications will not be a single crystal but polycrystalline, and therefore, grain size and grain boundary‐dependent scattering will further degrade the transport properties.