Stuck-open testable scan-based CMOS sequential circuits

A testing methodology for applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits is presented. This method requires shifting in only one pattern and requires no special latches in the scan chain. Sufficient conditions for robust testability of all single field-effect transistor (FET) stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. This technique leads to realizations with at most two additional inputs and some additional FET's in the first-level gates     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

Recursive Pseudo-Exhaustive Two-Pattern Generation

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In $(n, k)$-adjacent bit pseudo-exhaustive test sets, all $2^{k}$ binary combinations appear to all adjacent $k$-bit groups of inputs. With recursive pseudoexhaustive generation, all $(n, k)$-adjacent bit pseudoexhaustive tests are generated for ${k}leq{n}$ and more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern $(n, k)$-adjacent bit pseudoexhaustive tests for all ${k}leq{n}$. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.      

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.     

Multiple Scan Chain Design for Two-Pattern Testing

Non-standard fault models often require the application of two-pattern testing. A fully-automated approach for generating a multiple scan chain-based architecture is presented so that two-pattern test sets generated for the combinational core can be applied to the sequential circuit. Test time and area overhead constraints are considered.     

Fast robust correlation.

A new, fast, statistically robust, exhaustive, translational image-matching technique is presented: fast robust correlation. Existing methods are either slow or non-robust, or rely on optimization. Fast robust correlation works by expressing a robust matching surface as a series of correlations. Speed is obtained by computing correlations in the frequency domain. Computational cost is analyzed and the method is shown to be fast. Speed is comparable to conventional correlation and, for large images, thousands of times faster than direct robust matching. Three experiments demonstrate the advantage of the technique over standard correlation.     

Robust hybrid beamforming design for millimeter-wave massive MIMO systems

Hybrid analog-digital beamforming is recognized as a promising solution for a practical implementation of massive multiple-input multiple-output(MIMO) systems based on millimeter-wave(mmWave) technology. In view of the overwhelming hardware cost and excessive power consumption and the imperfection of the channel state information(CSI), a robust hybrid beamforming design is proposed for the mmWave massive MIMO systems, where the robustness is defined with respect to imperfect knowledge or error of the CSI at the transmitter due to limited feedback and/or imperfect channel estimation. Assuming the errors of the CSI are bounded, the optimal hybrid beamforming design with robustness is formulated to a mean squared error(MSE) minimization problem. An iterative semidefinite programming(SDP) based algorithm is proposed to obtain the beamforming matrices. Simulation results show that the proposed robust design can provide more than 4 dB performance gain compared to that of non-robust design.     

一种鲁棒的单载波频域均衡器

单载波频域均衡(SC-FDE)技术具有发送信号低峰均功率比的优势,是新一代通信3GPP-LTE/LTE-Advanced上行链路的关键技术之一。针对非理想信道估计,基于信道估计误差的统计模型,提出了一种联合频域均衡和时域判决反馈的鲁棒接收均衡器。以最小化均方误差(MSE)为最优准则,推导了均衡器的系数和均方误差的表达式。仿真结果表明,这种鲁棒的混合均衡器在非理想信道估计下较传统均衡器具有显著的性能提升。     

下行链路广播信道能效优化鲁棒波束成形算法

针对多天线广播下行链路通信系统,研究了一种鲁棒能效联合波束成形和功率分配算法。首先,鲁棒能效优化问题描述为满足一定功率约束的系统和速率与系统消耗之比的最大化优化问题。其次,利用分数规划理论及用户速率与最小均方误差之间的关系,把所描述的分数规划优化问题转化成参数化多项式优化问题。然后,利用拉格朗日对偶及单调优化理论,提出了一种有效的鲁棒能效优化算法。数值仿真结果表明,相对于传统的非鲁棒能效优化算法,所提鲁棒能效优化算法可获得明显的能效性能增益。      

一种有效的双矢量测试BIST实现方案

文章提出了一种简单有效的双矢量测试BIST。实现方案．其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法，该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测，证明了该方案在计算量和硬件开销方面的优越性。     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

A Stochastic Approximation Method with Enhanced Robustness for Crosstalk Cancellation

The objective of acoustic crosstalk cancellation is to use loudspeakers to deliver prescribed binaural signals (that reproduce a particular auditory scene) to a listener's ears, which is useful for 3-D audio applications. In practice, the actual transfer function matrix will differ from the design matrix, because of either the listener's head movement or rotation, etc. Crosstalk cancellation system (CCS) is very non-robust to these perturbations. Generally, in order to improve the robustness of CCS, several pairs of loudspeakers are needed whose position varies continuously as frequency varies. With the help of assumed stochastic analysis, we propose a stochastic robust approximation crosstalk cancellation method based on random perturbation matrix modeling the variations of the transfer function matrix. Under the free-field condition, simulation results demonstrate the effectiveness of the proposed method.     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

非完备杂波先验知识场景下MIMO-STAP稳健波形设计

本文考虑了色高斯干扰条件下MIMO STAP稳健波形优化问题以提高非完备杂波先验知识条件下多输入多输出（MIMO）雷达体制下空时自适应处理（STAP）最坏情况下探测性能。由于高斯干扰（包括杂波、干扰以及热噪声）场景下最大化系统输出信干噪比（SINR）等价于最大化MIMO STAP检测性能,因而在本文所建立杂波协方差估计误差的模型基础上,总功率发射以及参数不确定凸集约束下,经推导可得稳健波形优化问题。为求解得到的复杂非线性问题,本文提出了一种迭代算法以优化发射波形相关阵（WCM）从而最大化凸不确定集上最差情况下的输出SINR进而改善最差情况下MIMO STAP的检测性能。通过利用对角加载（DL）方法,所提算法中的每个迭代步骤皆可表示为能获得高效求解的半定规划（SDP）问题。与非稳健方法及非相关波形相比,数值实验验证了本文所提方法的有效性。      

Robust joint optimization for MIMO AF multiple-relay systems with correlated channel uncertainties

In the paper, robust joint optimization of the source/relays precoders and destination equalizer is proposed for non-regenerative dual-hop multiple-input multiple-output (MIMO) amplify-and-forward (AF) multiple-relay systems with correlated channel uncertainties. By taking the imperfect channel state information (CSI) into consideration, the robust transceiver/relays joint optimization is developed based on the minimum mean-squared error (MMSE) criterion under individual power constraints at the source and relays. The optimization problem of precoding and amplifying matrices under power constraints belongs to neither concave nor convex so that a nonlinear matrix-form conjugate gradient (MCG) algorithm is applied to explore local optimal solutions. Simulation results illustrate that the robust transceiver/relays joint architecture for an AF-MIMO multiple-relay system outperforms the non-robust transceiver/relays design.     

RLP-AGMC: Robust label propagation for saliency detection based on an adaptive graph with multiview connections

There have been remarkable improvements in the salient object detection in the recent years. During the past few years, graph-based saliency detection algorithms have been proposed and made advances. Nevertheless, most of the state-of-the-art graph-based approaches are usually designed with low-level features, misleading assumption, fixed predefined graph structure and weak affinity matrix, which determine that they are not robust enough to handle images with complex or cluttered background.In this paper, we propose a robust label propagation-based mechanism for salient object detection throughout an adaptive graph to tackle above issues. Low-level features as well as deep features are integrated into the proposed framework to measure the similarity between different nodes. In addition, a robust mechanism is presented to calculate seeds based on the distribution of salient regions, which can achieve desirable results even if the object is in contact with the image boundary and the image scene is complex. Then, an adaptive graph with multiview connections is constructed based on different cues to learn the graph affinity matrix, which can better capture the characteristics between spatially adjacent and distant regions. Finally, a novel RLP-AGMC model, i.e. robust label propagation throughout an adaptive graph with multiview connections, is put forward to calculate saliency maps in combination with the obtained seed vectors. Comprehensive experiments on six public datasets demonstrate the proposed method outperforms fourteen existing state-of-the-art methods in terms of various evaluation metrics.     

Robust Interference Management via Linear Precoding and Linear/Non-Linear Equalization

This work studies the robust design of linear precoding and linear/ non-linear equalization for multi-cell MIMO systems in the presence of imperfect channel state information (CSI). A worst-case design approach is adopted whereby the CSI error is assumed to lie within spherical sets of known radius. First, the optimal robust design of linear precoders is tackled for a MIMO interference broadcast channel (MIMO-IBC) with general unicast/multicast messages in each cell and operating over multiple time-frequency resources. This problem is formulated as the maximization of the worst-case sum-rate assuming optimal detection at the mobile stations (MSs). Then, symbol-by-symbol non-linear equalization at the MSs is considered. In this case, the problem of jointly optimizing linear precoding and decision-feedback (DF) equalization is investigated for a MIMO interference channel (MIMO-IC) with the goal of minimizing the worst-case sum-mean squared error (MSE). Both problems are addressed by proposing iterative algorithms with descent properties. The algorithms are also shown to be implementable in a distributed fashion on processors that have only local and partial CSI by means of the Alternating Direction Method of Multipliers (ADMM). From numerical results, it is shown that the proposed robust solutions significantly improve over conventional non-robust schemes in terms of sum-rate or symbol error rate. Moreover, it is seen that the proposed joint design of linear precoding and DF equalization outperforms existing separate solutions.     

Robust Collaborative-Relay Beamforming

Relay communications is a promising technique to extend the range of wireless communications by forwarding the message from the sender to the intended destination. While fixed or variable-power relays have been previously investigated, this paper addresses the collaborative use of variable-phase variable-power amplify-and-forward (AF) relays for robust beamforming, with the aid of imperfect channel state information (CSI) at the sender. In particular, the maximization of the worst-case signal-to-noise ratio (SNR) at the destination terminal is studied under a bounded spherical region for the norm of the CSI error vector from the relays to the destination. Our main contribution is that we prove, under a condition on the quality of the estimated CSI, the robust-optimal collaborative-relay beamforming (CRBF) can be obtained by S-procedure and rank relaxation techniques. In addition, a distributed algorithm is developed by examining the structure of the optimal CRBF solution. Results demonstrate a significant gain of CRBF over non-robust approaches.