一种有效的双矢量测试BIST实现方案

文章提出了一种简单有效的双矢量测试BIST。实现方案．其硬件主要由反馈网络可编程且种子可重置的LF—SR和映射逻辑两部分构成。给出了一种全新的LPSR最优种子及其反馈多项式组合求取算法，该算法具有计算简单且容易实现的特点。最后。使用这种BIST、方案实现了SoC中互联总线间串扰故障的激励检测，证明了该方案在计算量和硬件开销方面的优越性。     

On robust two-pattern testing of one-dimensional CMOS iterative logic arrays

In this paper a graph model and a method to construct robust (for the first time in open literature) as well as non-robust two-pattern tests for one-dimensional iterative logic arrays (ILAs) are presented. Exploring the graph structure we can find two-pattern tests that can be applied with a constant or linear number of test vectors to all the ILA cells. Such tests are subsequently characterized as robust or non-robust two-pattern tests.     

Testable design of BiCMOS circuits for stuck-open fault detectionusing single patterns

Single BJT BiCMOS devices exhibit sequential behavior under transistor stuck-OPEN (s-OPEN) faults. In addition to the sequential behavior, delay faults are also present. Detection of s-OPEN faults exhibiting sequential behavior needs two-pattern or multipattern sequences, and delay faults are all the more difficult to detect. A new design for testability scheme is presented that uses only two extra transistors to improve the circuit testability regardless of timing skews/delays, glitches, or charge sharing among internal nodes. With this design, only a single vector is required to test for a fault instead of the two-pattern or multipattern sequences. The testable design scheme presented also avoids the requirement of generating tests for delay faults     

一种基于双模结构的预测器

分支预测是限制微处理器性能提高的一个重要因素,因此也一直是微处理器设计研究的重点.文中提出了一种对动态两级自适应分支预测进行改进的新方法,即基于双模结构的双模预测器.它能同时根据指令转移间相关和转移内相关进行转移预测,从而获得更高的转移预测精度.     

Recursive Pseudo-Exhaustive Two-Pattern Generation

Pseudo-exhaustive pattern generators for built-in self-test (BIST) provide high fault coverage of detectable combinational faults with much fewer test vectors than exhaustive generation. In $(n, k)$-adjacent bit pseudo-exhaustive test sets, all $2^{k}$ binary combinations appear to all adjacent $k$-bit groups of inputs. With recursive pseudoexhaustive generation, all $(n, k)$-adjacent bit pseudoexhaustive tests are generated for ${k}leq{n}$ and more than one modules can be pseudo-exhaustively tested in parallel. In order to detect sequential (e.g., stuck-open) faults that occur into current CMOS circuits, two-pattern tests are exercised. Also, delay testing, commonly used to assure correct circuit operation at clock speed requires two-pattern tests. In this paper a pseudoexhaustive two-pattern generator is presented, that recursively generates all two-pattern $(n, k)$-adjacent bit pseudoexhaustive tests for all ${k}leq{n}$. To the best of our knowledge, this is the first time in the open literature that the subject of recursive pseudoexhaustive two-pattern testing is being dealt with. A software-based implementation with no hardware overhead is also presented.      

LFSR-Based Deterministic TPG for Two-Pattern Testing

This paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.     

AC strength of a pattern generator

The AC strength of a pattern generator is the fraction of the exhaustive two-pattern count that it can apply to the logic given sufficient time. It is a measure that allows assessing how well a pattern generator can serve in applying AC test vectors to the logic. Generators with high AC strengths tend to perform better than generators with low AC strengths.Special generators with high AC strengths can be designed with a considerable penalty of hardware overhead. An alternative to designing special pattern generators that can serve well during AC test is to separate the inputs of the logic fed by the generator, so that no two inputs belonging to the same output cone in the logic are connected to adjacent stages of the generator. This input separation will facilitate an effective AC test, and will not suffer from the high overhead that the special generators suffer from.This paper introduces the notion of the AC strength of a pattern generator and proposes the input separation scheme that will allow an efficient AC test to be performed on the logic.     

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.     

Stuck-open testable scan-based CMOS sequential circuits

A testing methodology for applying two-pattern tests for stuck-open faults in scan-testable CMOS sequential circuits is presented. This method requires shifting in only one pattern and requires no special latches in the scan chain. Sufficient conditions for robust testability of all single field-effect transistor (FET) stuck-open faults and design techniques for robustly scan-testable CMOS sequential circuits are presented. This technique leads to realizations with at most two additional inputs and some additional FET's in the first-level gates     

Characterization of a photoresist with wavelength selected tone

The line edge profile simulation of a tone-switching resist system, obtained from the dissolution model of dual-sensitized, novolak-based resist in aqueous developer, is described. The model incorporates the actinic response of both a positive and a negative sensitizer in a two-pattern lithographic process that simultaneously exposes the same resist film. These response data are combined with dissolution rate measurements to establish a model for the resist and carry out SAMPLE simulation of resist line edge profiles for contact and projection printing. The model predictions are compared with SEM micrographs of exposed resist features     

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2 ⁿ × (2 ⁿ – 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.     

Scalable Delay Fault BIST for Use with Low-Cost ATE

We present a BIST architecture based on a Multi-Input Signature Register (MISR) expanding single input vectors into sequences, which are used for testing of delay faults. Input vectors can be stored on-chip or in the ATE; in the latter case, a low speed tester can be employed though the sequences are applied at-speed to the block-under-test. The number of input vectors (and thus the area demand on-chip or ATE memory requirements) can be traded for the test application time.We propose several methods for generating input vectors, which differ in test application time, area requirements and algorithm run-time. As all of them require only a two-pattern test as input, IP cores can be handled by these methods.The block-under-test can be switched off for some amount of time between application of consecutive input vectors. We provide arguments why this approach may be the only way to meet thermal and power constraints. Furthermore, we demonstrate how the BIST scheme can use these cool-down breaks for re-configuration.     

Chiba Scan Delay Fault Testing with Short Test Application Time

Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT.     

Cell delay fault testing for iterative logic arrays

C-testable iterative logic arrays for cell-delay faults are proposed. A cell delay fault occurs if and only if an input transition can not be propagated to the cell's output through a path in the cell in a specified clock period. The set of single-path propagation, hazard-free robust tests that completely check all the paths in a cell is first derived, and then necessary conditions for sending this test set to each cell in the array and simultaneously propagating the fault effects to the primary outputs are given. Test set minimization can be solved in a similar way as for the fault cover problem. We use the pipelined array multiplier as an example, and show that it is C-testable with 214 two-pattern tests. With a small number of additional patterns, all the combinational faults can be detected pseudoexhaustive.     

数字电路测试程序设计

为了更好地满足生产质量要求,严格测试电路的全部功能及交直流参数是十分必要的。在多年测试实践基础上,文章提出了数字电路测试程序设计的概要。随着集成电路的集成度越来越高,功能更加强大,测试向量越来越大,测试时间也越来越长。为了降低测试成本,Teradyne J750测试系统以测试速度快的特点,顺应测试行业的发展,在行业中得到了广泛的应用。文中以74HC123芯片为例,对于一些数字电路关键测试技术在Teradyne J750测试机上的调试做出了较详细的阐述。     

An Integrated Framework for the Design and Optimization of SOC Test Solutions

We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for the final solution. The framework deals with test scheduling, test access mechanism design, test sets selection, and test resource placement. Our approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests and power consumption. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. We have made an implementation of the proposed heuristic used for the early design space exploration and an implementation based on Simulated Annealing for the extensive optimization. Experiments on several benchmarks and industrial designs show the usefulness and efficiency of our approach.     

基于8852的雷达领域可测性技术的探究

雷达领域插件级设计的模块化、软件化、标准化、继承性的推广使得针床测试台的性能价格比得以提高,我们基于美国TERADYNE公司的"Spectrum 8852"自动测试设备,完成了6个品种插件的测试夹具、软件开发.夹具开发的自动化程度高、价格低;软件上运用4种测试理念对插件进行全方位测试,互相覆盖、互相补充,提高了故障覆盖率和准确率,具有推广使用价值.同时也给出了一些我们在开发过程中遇到的、有关可测试性设计考虑的建议.     

Structural Fault Based Specification Reduction for Testing Analog Circuits

Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is proposed and demonstrated. It starts with first deriving relationships between specifications and parameter variations of the circuit-under-test (CUT) and then reduces specifications by considering bounds of parameter variations. A statistical approach by taking into account of circuit fabrication process fluctuation is also employed and the result shows that the specification reduction depends on the testing confidence. A continuous-time state-variable benchmark filter circuit is applied with this methodology to demonstrate the effectiveness of the approach.     

Efficient Test Data Compression and Low Power Scan Testing in SoCs

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.     

软件的单元测试方法

软件测试是软件质量保障的技术关键,而单元测试是软件开发过程中不可缺少的部分,是其他测试的基础。重点介绍了单元测试的方法,并结合实际说明了这些方法的技术应用。