基于4T结构的高灵敏度CMOS图像传感器设计

基于0.35μm工艺,设计了应用于低光照环境下的低噪声、高灵敏度CMOS图像传感器。该图像传感器采用PPD 4T像素结构,像素阵列512×512,包含列级运放、水平移位寄存器、逻辑控制单元、单斜率模数转换器和偏置电路等模块。通过采用低噪声PPD 4T像素结构、低噪声列级放大器电路结构,以及对版图的优化设计等措施实现了低噪声、高灵敏度的CMOS图像传感器设计。     

应用于微小卫星的CMOS图像传感器芯片设计

针对小卫星以至微纳卫星领域的应用需求,文章对具有抗辐照能力的CMOS图像传感器的芯片架构和关键技术进行了研究,着重对行列选电路、低噪声信号读出、可编程增益放大器和片上ADC等电路设计技术进行了分析和仿真验证.基于0.35 μm CMOS抗辐照技术和工艺开展了芯片的关键电路仿真、设计和整体版图设计验证.流片后的测试结果表明,该CMOS图像传感器具有高动态、低噪声和抗辐照特点,其噪声电子为42 e-,动态范围为69 dB,当辐射总剂量大于100 krad(Si)时,器件噪声指标符合预期.     

CMOS图像传感器的发展现状及关键技求探讨

介绍了国外CMOS图像传感器技术的发展状况,比较了CMOS图像传感器技术与CCD图像传感器技术的优缺点,分析了国内CMOS图像传感器技术的研究现状,探讨了CMOS图像传感器研究的关键技术。     

CMOS图像传感器的发展现状及关键技术探讨

介绍了国外CMOS图像传感器技术的发展状况，比较了CMOS图像传感器技术与CCD图像传感器技术的优缺点，分析了国内CMOS图像传感器技术的研究现状，探讨了CMOS图像传感器研究的关键技术。     

全局快门像素技术和CMoS图像传感器形成强大的技术组合

传统上,全局快门像素技术主要用于CCD图像传感器。由于CMOS图像传感器的不断普及,且由于机器视觉、电影制作、工业、汽车和扫描应用要求必须以高图像品质捕捉快速移动的物体,图像传感器供应商Aptina公司已经致力于克服在CMOS图像传感器上使用全局快门像素技术的相关传统障碍。     

8MP图像传感器为智能手机带来高清视频和高质量图像

Aptina日前推出采用Aptina A-PixHS技术的8百万像素(MP)AR0833图像传感器。Aptina公司手机、平板电脑和游戏事业部市场总监Venkat Puntambekar介绍说,Aptina的CMOS图像传感器解决方案具有业界领先的技术,可针对不同的市场应用。一是Aptina A-PixHS技术。该技术融合了Aptina的背照式(BSI)像素技术和先进的高速传感器架构,使新型高性能摄像头成为可能。BSI像素技术翻转传感器以使照片灵敏区更靠近镜头并采用Aptina A-Pix技术中先进的工程设计技术,     

低噪声CMOS图像传感器的重点专利分析

随着大规模集成电路设计和信号处理技术的提高,CMOS图像传感器日益受到重视,成为固态图像传感器的研究热点,但是噪声仍是制约CMOS图像传感器发展的重要因素之一.针对低噪声的CMOS图像传感器技术领域的专利文献,给出了该领域主要申请人的申请量分布图,并对该领域的重要专利进行分析,介绍了前5位重要专利的技术特点.     

采用增强型像素构架的200万像素CMOS图像传感器 在高分辨率下高速撷取图像

ADCC-4050是1／4英寸光学格式CMOS图像传感器。其采用了Avago Technologies的增强型像素架构和第八代图像信号传输处理技术，改善了图像输出延迟的现象。     

APS CMOS图像传感器复位电路的设计研究

本文分析了APS CMOS图像传感器传统像素复位电路引起的动态范围缩小、固定图像噪音增大和图像滞后等问题.比较了两种复位电路改进方案的优势与不足.提出了采用电荷泵电路设计APS CMOS图像传感器复位电路的新方案.该方案增加了CMOS图像传感器的动态范围,消除了复位引起的固定图像噪音和图像滞后,避免了前两种方案的不足.所有的电路仿真均在CHRT 0.35 μm工艺基础上完成.     

CMOS图像传感器固定模式噪声抑制新技术。

针对有源像素(APS)CMOS图像传感器中的固定模式噪声(FPN),设计了一种动态数字双采样的噪声抑制新技术;该技术比普通双采样技术具有更佳的抑制效果,其电路结构简单,适合于像素尺寸不断缩小的CMOS图像传感器发展趋势。通过MPW计划,采用Chartered0.35μmCMOS工艺制作了测试ASIC芯片,试验结果表明动态数字双采样技术有效抑制了FPN噪声。     

Object location and centroiding techniques with CMOS active pixel sensors

A system based on a pixel-parallel CMOS active pixel sensor architecture is demonstrated for capturing the location and approximate size of an object. The object is distinguished from the background by a global threshold. Three prototype sensors are implemented in standard CMOS technologies. In the first, a high fill factor three-transistor pixel with integral comparator is demonstrated. It is shown that performance of this sensor is limited by device nonuniformities, so a novel in-pixel fixed-pattern noise correction circuit using a single capacitor is demonstrated in the second sensor. The system concept is further enhanced by a cumulative cross section readout architecture which provides additional information regarding the object with little reduction in speed. The application of these systems to centroid determination using multiple thresholds is discussed.     

1400万像素CMOS传感器高速读出及信号采集的研究

面阵图像传感器的读出电路和信号采集电路是影响图像信号性能的关键部分之一。文章介绍了采用2路双通道AD及USB2．0实现了1400万像素高分辨率CMOS面阵传感器的大动态范围，低读出噪音的高速信号采集系统，并对系统的传输速度、分辨率、图像噪音、光强测量稳定性、近红外响应等进行了实验研究。     

A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification

This paper briefly examines the pros and cons of CMOS pulse-frequency-modulation (PFM) digital pixel sensors. A pulse-frequency-modulation digital pixel sensor with in-pixel amplification is proposed to improve the resolution of the pixel sensor at low illumination. The proposed PFM digital pixel sensor offers the characteristics of a reduced integration time when the level of illumination is low with the fill factor comparable to that of PFM digital pixel sensors without in-pixel amplification. The proposed digital image sensor has been designed in TSMC- 1.8 V CMOS technology and validated using Spectre from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the dynamic range of the proposed PFM digital pixel sensor with in-pixel amplification is 20 dB larger as compared with that of PFM digital pixel sensors without in-pixel amplification. The increased dynamic range is obtained in the low illumination condition where PFM digital pixel sensors without in-pixel amplification cease the operation due to the low photo current.     

A CMOS Image Sensor With In-Pixel Buried-Channel Source Follower and Optimized Row Selector

This paper presents a CMOS imager sensor with pinned-photodiode 4T active pixels which use in-pixel buried-channel source followers (SFs) and optimized row selectors. The test sensor has been fabricated in a 0.18-mum CMOS process. The sensor characterization was carried out successfully, and the results show that, compared with a regular imager with the standard nMOS transistor surface-mode SF, the new pixel structure reduces dark random noise by 50% and improves the output swing by almost 100% without any conflicts to the signal readout operation of the pixels. Furthermore, the new pixel structure is able to drastically minimize in-pixel random-telegraph-signal noise.     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

Temporal Noise Analysis and Reduction Method in CMOS Image Sensor Readout Circuit

Temporal noise such as thermal and low-frequency noise (LF noise) in the CMOS imager readout circuit has been analyzed. In addition, the effect of correlated double sampling operation on the noise was included. We have derived an analytical noise equation for the specified readout circuit, and confirmed its validity by comparing it with the simulation result. Thermal noise model which is accurate in short-channel devices operating in saturation region was used. Since the in-pixel devices (source follower and selection transistor) of the readout circuit are relatively small in size, and thus exhibits random telegraph signal (RTS) noise, both 1/f and RTS noise were considered for their LF noise. Based on the analyzed noise components, we presented the noise reduction method by adjusting the transistors sizes in the readout circuit.     

Correlated multiple sampling technique - a discrete Fourier Transform analysis aimed for CMOS image sensors

Modern CMOS image sensors generally face difficulties in limiting the noise effect of their readout circuits. The existing noise sources range from spatial to temporal noise, such as the thermal, the flicker, and the random telegraph signal noise sources. The noise sources and the device’s image quality issues become more evident when targeting design goals, such as high resolution and high frame-rate. This paper focuses on the theoretical derivation of the Correlated Multiple Sampling technique by means the Discrete Fourier Transform in which it explicitly includes the noise contamination process during the image sensor readout operation. The purpose of the proposed approach is to deepen the underlying multiple sampling process role in low noise systems and how beneficial this technique is in suppressing the noise contamination, as such proposing a more intuitive way to understand the method.

     

Design and evaluation of current-mode image sensors in CMOS-technology

Three different current-mode-output CMOS image sensor structures comprising of a pixel cell and an appropriate readout circuit have been analyzed and compared with regard to their noise behavior, fixed-pattern noise (FPN), and the dynamic range. First, a standard integrating pixel cell with a readout circuit containing a voltage-to-current converter is proposed. Second, a pixel cell based on a switched current cell is analyzed. The third sensor cell uses a feedback loop to control the reverse bias voltage of the photodiode to reduce the settling time of the pixel cell and the influence of the photodiodes's dark current. The necessary amplifier is partly located in the pixel cell and partly in the readout circuit. In all sensors, correlated double sampling is used to suppress the FPN.     

New signal readout method for ultrahigh-sensitivity CMOS image sensor

We propose a new signal readout method that uses a charge-transfer circuit. Its application is to an ultrahigh-sensitivity CMOS image sensor on which an avalanche-mode photoconductive film is overlaid. The charge-transfer circuit makes it possible to obtain high signal-to-noise ratio features by transferring signal charges accumulated in each photodiode to a parasitic capacitance that is small compared with the photodiode capacitance. A 138 /spl times/ 138 passive-pixel prototype sensor that had the charge-transfer circuit in each column was fabricated and tested. The prototype's column-to-column fixed-pattern noise and random noise were, respectively, 56.7 and 58.4 dB below the saturation signal level, which demonstrated its potential as a signal readout circuit for a next-generation ultrahigh-sensitivity CMOS image sensor.     

Readout circuit for CMOS active pixel image sensor

The design and simulation results of a new readout circuit for a CMOS active pixel image sensor are presented. This scheme removes the fixed pattern noise and reduces the signal degradation while offering an increase in readout speed, compared with the conventional approach