Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.     

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.     

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Going vertical as in 3-D IC design, reduces the distance between vertical active silicon dies, allowing more dies to be placed closer to each other. However, putting 2-D IC into three-dimensional structure leads to thermal accumulation due to closer proximity of active silicon layers. Also the top die experiences a longer heat dissipation path. All these contribute to higher and non-uniform temperature variations in 3-D IC; higher temperature exacerbates negative bias temperature instability (NBTI). NBTI degrades CMOS transistor parameters such as delay, drain current and threshold voltage. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security. We demonstrated that a hardware intruder could leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. In this paper we provide a detailed analysis on how tiers of 3-D ICs can be subject to exacerbated NBTI. We proposed to embed threshold voltage extractor circuit in conjunction with a novel NBTI-mitigation scheme as a countermeasure against such anticipated Trojans. We validated through post-layout and Monty Carlo simulations using 45 nm technology that our proposed solution against NBTI effects can compensate the NBTI-effects in the 3-D ICs. With the area overhead of 7% implemented in Mod-3 counter, our proposed solution can completely tolerate NBTI-induced degraded threshold voltage shift of up to 60%.     

Maximising energy efficiency in 3D multicore systems: a formalised approach

Three-dimensional integrated circuits (3D ICs) present an intriguing challenge for both circuit and system engineers due to their diverse cooling efficiency among the stacked dies. Several recent proposals advocate multiple techniques for thermal management of 3D ICs at different levels of the design, while operating within the confines of thermal heterogeneity. In this article, we analyse for the first time, the role of thermal heterogeneity on the energy efficiency of the system by incorporating temperature dependent leakage power. We develop a novel convex optimisation framework to optimise the energy efficiency in 3D ICs incorporating: (a) leakage aware thermal provisioning using temperature dependent full-chip leakage model, (b) heat flow in vertically stacked systems using a grid based compact thermal model and (c) a concrete application for workload provisioning in 3D multicore systems. Detailed simulation-based experiments with our proposed optimisation framework shows 5–17% improvement in the energy efficiency of a typical multicore system organised as 3D stacked dies.     

Thermal design and simulation of bipolar integrated circuits

Keeping device operating temperatures within reasonable limits is necessary for reliability of all ICs and important for achieving the expected performance for many ICs. GaAs heterojunction bipolar transistors (HBTs) offer high speed and good device matching characteristics that are attractive for many high-speed circuits, but they are more susceptible than other IC technologies to the unexpected generation of very high junction temperatures. The reasons for this tendency are discussed, and an HBT sample-and-hold (S/H) circuit that had device temperature rises of over 300°C is described. To address this problem, a new thermal simulation tool called ThCalc was created. ThCalc calculates the temperature profile of an IC and runs fast enough to allow calculations on a whole chip. ThCalc was used to redesign the S/H IC to reduce the largest temperature rise by a factor of 2.7 with a minimal impact on circuit size     

3-D ICs: a novel chip design for improving deep-submicrometerinterconnect performance and systems-on-chip integration

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined     

A copper/polyimide Metal-base packaging technology

A unique substrate MCPM (Mitsubishi Copper Polyimide Metal-base) technology has been developed by applying our basic copper/polyimide technology.¹ This new substrate technology MCPM is suited for a high-density, multi-layer, multi-chip, high-power module/package, such as used for a computer. The new MCPM was processed using a copper metal base (110 × 110 mm), full copper system (all layers) with 50-μm fine lines. As for pad metallizations for the IC assembly, we evaluated both Ni/Au for chip and wire ICs and solder for TAB ICs. The total number of assembled ICs is 25. To improve the thermal dispersion, copper thermal vias are simultaneously formed by electro-plating. This thermal via is located between the IC chip and copper metal base, and promotes heat dispersion. We employed one large thermal via (4.5 mm^?) and four small vias (1.0 mm^?) for each IC pad. The effect of thermal vias and/or base metal is simulated by a computer analysis and compared with an alumina base substrate. The results show that the thermal vias are effective at lowering the temperature difference between the IC and base substrate, and also lowering the temperature rise of the IC chip. We also evaluated the substrate’s reliability by adhesion test, pressure cooker test, etc.     

Analysis of thermal impedance for conventional and beam lead IC chips

The thermal impedance of conventional and beam lead IC packages is evaluated from the partial differential equations, which govern the temperature and heat flow within the chip and substrate, and transmission line analogy. The mounting and the geometry dependance of the thermal impedance for various heat sink and chip sizes are presented for both beam lead and conventional IC packages. The variation of thermal impedance with the number of leads and the various Ceramic sizes is shown for the beam lead IC chip.The lumped and the distributed heat sources have been considered for the different mounting structures.     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.     

Cool Chips: Opportunities and Implications for Power and Thermal Management

Alongside innovative device, circuit, and microarchitecture level techniques to alleviate power and thermal problems in nanoscale CMOS-based integrated circuits (ICs), chip cooling could be an effective knob for power and thermal management. This paper analyzes IC cooling while focusing on the practical temperature range of operation. Comprehensive analyses of chip cooling for various nanometer scale bulk-CMOS and silicon-on-insulator (SOI) technologies are presented. Unlike all previous works, this analysis employs a holistic approach (combines device, circuit and system level considerations) and also takes various electrothermal couplings between power dissipation, operating frequency and die temperature into account. While chip cooling always gives performance gain at the device and circuit level, it is shown that system level power defines a temperature limit beyond which cooling gives diminishing returns and an associated cost that may be prohibitive. A scaling analysis of this temperature limit is also presented. Furthermore, it is shown that on-chip thermal gradients cannot be mitigated by global chip cooling and that localized cooling can be more effective in removing hot-spots.     

Manufacturing ICs the neural way

To offset the enormous investment of semiconductor companies, chip manufacturers must innovate to a greater degree in the fabrication processes themselves. The aim is to employ the latest computer hardware and software developments-namely, computer-integrated manufacturing of integrated circuits (or IC-CIM)-to optimize the cost-effectiveness of IC manufacture, much as computer-aided design (CAD) revolutionized the economics of circuit design. Here, the author describes how neural networks have recently emerged as a powerful aid in a computer-integrated manufacturing of ICs. Such neural networks help engineers infer subtle input-output relationships     

Three-dimensional IC trends

VLSI will be reaching to the limit of minimization in the 1990s, and after that, further increase of packing density or functions might depend on the vertical integration technology. Three-dimensional (3-D) integration is expected to provide several advantages, such as 1) parallel processing, 2) high-speed operation, 3) high packing density, and 4) multifunctional operation. Basic technologies of 3-D IC are to fabricate SOI layers and to stack them monolithically. Crystallinity of the recrystallized layer in SOI has increasingly become better, and very recently crystalaxis controlled, defect-free single-crystal area has been obtained in chip size level by laser recystallization technology. Some basic functional medels showing the concept or image of a future 3-D IC were fabricated in two or three stacked active layers. Some other proposals of subsystems in the application of 3-D structure, and the technical issues for realizing practical 3-D IC, i.e., the technology for fabricating high-quality SOI crystal on complicated surface topology, crosstalk of the signals between the stacked layers, total power consumption and cooling of the chip, will also be discussed in this paper.     

超薄芯片叠层封装器件热可靠性分析

采用通用有限元软件MSC.Marc,模拟分析了一种典型的多层超薄芯片叠层封装器件在经历回流焊载荷后的热应力及翘曲分布情况,研究了部分零件厚度变化对器件中叠层超薄芯片翘曲、热应力的影响。结果表明:在整个封装体中,热应力最大值(116.2 MPa)出现在最底层无源超薄芯片上,结构翘曲最大值(0.028 26 mm)发生于模塑封上部边角处。适当增大模塑封或底层无源芯片的厚度或减小底充胶的厚度可以减小叠层超薄芯片组的翘曲值;适当增大底层无源超薄芯片的厚度(例如0.01 mm),可以明显减小其本身的应力值10 MPa以上。     

3-D MCM 的种类

介绍了3-D MCM封装的种类,其中包括芯片垂直互连和2-D MCM的垂直互连。芯片的垂直互连,包括芯片之间通过周边进行互连,以及芯片之间通过贯穿芯片进行垂直互连(面互连);2-D MCM模块垂直互连,包括2-D MCM之间通过周边进行互连,以及面互连的模式。     

System-level performance evaluation of three-dimensional integratedcircuits

In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rent's rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution). Two limiting cases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as clock frequency, chip area, etc., are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs. The technology requirement for interconnects in 3-D integration is also discussed     

A novel switchable pin method for regulating power in chip-multiprocessor

Transistor scaling has allowed a large number of circuits to be integrated into integrated circuit (IC) chips implemented in nanometer CMOS technology nodes. However, dark silicon which signifies for under-utilized circuitry will become dominant in future chips due to limited thermal design power (TDP). Furthermore, large voltage loss due to complex routing and placement will also degrade the performance of ICs. In addition, effectively managing power dissipation in a packaged chip is one of the major issues of IC design. Previous work done by our group mainly focused on RCL simulation and elementary IC simulation, this work not only builds on power delivery network (PDN), but also designs switchable pin working for two cores at the layout level. The essence of our idea is to supply power to the chip using traditional I/O pads. In order to balance power supply and I/O bandwidth, we set several groups of parallel switchable pins between the core and memory such that I/O pads can dynamically switch between two modes which are data transmission and power supply. To remove the risk that large current going through I/O pad breaks down the pad frame, we redesigned traditional I/O pad to operate in bi-direction. Using TSMC CMOS 180 nm process for the design and simulation, our test results show that the proposed switchable pin can well compensate voltage loss in chip multiprocessor, and transfer time of two modes is very short. For data transmission, we perform a sensitivity study to explore the impact brought by switchable pins. Our simulation results demonstrate that performance degradation is in acceptable range when the switchable pins are added to the chip-multiprocessor.     

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

In the system-on-a-chip (SOC) era, chip layouts of integrated circuit (IC) products become more and more compact for cost reduction. To save layout area for SOC chips, on-chip electrostatic discharge (ESD) protection devices or input/output (I/O) transistors placed under bond pads is a good choice. To ensure that this choice is practicable, a test chip with large size NMOS devices placed under bond pads had been fabricated in a 0.35-/spl mu/m 1P4M 3.3-V CMOS process for verification. The bond pads of this test chip had been drawn with different layout patterns on the interlayer metals for two purposes. One is to investigate the efficiency against bonding stress applied on the active devices under the bond pads. The other purpose is to reduce the parasitic capacitance of bond pads for high-speed or high-frequency circuit applications. DC characteristics of these devices placed under bond pads had been measured under three conditions: before wire bonding, after wire bonding, and after thermal reliability stresses. After assembly with wire bond package and thermal reliability stresses, the measured results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied to save layout area of IC products by realizing on-chip ESD protection devices or I/O transistors under the bond pads, especially for the high-pin-count SOC.     

Investigating the thermal response of a micro-optical shutter

The thermal analysis of a fully integrated micro-switch for surety applications will be presented. Specifically, this study focuses on the temperature increase of a micromachined optical shutter with spot heating from a solid-state laser. To analyze the shutter response, a "design-to-analysis" interface has been developed that generates an accurate three-dimensional (3-D) solid geometry from the two-dimensional (2-D) mask layout. By building the "design-to-analysis" interface, engineers can use this solid modeler to virtually prototype and verify a design, and to simulate the performance of micro-devices before fabrication. To determine the effects of thermal conductivity and contact resistance on the thermal response of this passively cooled device, a sensitivity study is also performed.     

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.      

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.