一种改进的数字乘积检波方法

数字乘积检波(DPD:Digital Product Detector)是一种工程实现数字正交解调的简便方法[1][2],该方法克服了模拟正交解调I、Q通道不平衡的缺点[1],在雷达中频或射频信号采样中得到了广泛应用.然而该方法获得的I、Q数据在时间上不同步,需要进行分数阶多相插值滤波修正[1]～[8],由于分数阶多相插值滤波器无法做到I、Q通道幅度和相位的同时匹配[2],其不匹配引入的镜像干扰对工作在极低信噪比下的车载前视步进频率雷达来说非常不利.本文从信号与系统基本原理[9]出发,对DPD方法进行改进,提出了一种不需要对I、Q数据进行分数阶多相插值滤波,就可以得到时间同步I、Q数据的正交解调方法,该方法简便灵活,容错性强,用低通滤波器代替分数阶多相插值滤波器,可以做到两个通道幅度和相位的同时匹配,可以很好地控制I、Q分量幅度和相位的一致性.     

数字合成孔径雷达中改善I/Q通道不平衡性的多相Kaiser滤波法

该文分析了数字合成孔径雷达正交相干检波的I,Q通道的不平衡性,给出了评价I/Q通道不平衡性的统一指标。为了改善数字合成孔径雷达I/Q通道的不平衡性,该文采用了一种新的方法内插多相Kaiser滤波法.研究表明,当多相Kaiser滤波器的阶数为16时,噪声旁瓣的抑制比为-74dB,相对瞬时频率误差为-1.18％。     

基于双中频并行采样的数字I/Q信号获取

针对大时宽带宽积信号模拟正交解调时难以工程实现的问题,提出了基于双中频并行采样的正交解调方法和结构。该方法和结构是模拟正交解调的推广,通过对包含相同回波信息的两路中频信号在特定时刻采样,以及对两采样序列作简单的符号转换来获取数字I/Q信号,解决了大时宽带宽积信号模拟正交解调时性能较差以及需要复杂的数字校正过程等问题,且易于工程实现与实时处理。误差分析表明,该方法和结构在大时宽带宽积信号时获取的数字I/Q信号性能优良。      

一种新型宽带接收机I/Q通道失配的数字校正方法

由于各种因素的影响,I/Q通道之间通常会发生失配现象,这会降低接收机的动态范围,进而影响接收机的性能。本文提出了一种宽带接收机中L/Q幅相误差校正的数字方法：首先通过一种时域方法以获得误差信息,籍此计算校正所需参数,再由Newton插值多项式构造滤波器组对I/Q信号进行滤波校正。仿真表明,这种数字校正方法能有效地提高宽带接收机I/Q通道的正交一致性。     

基于软件无线电多相滤波的数字正交变换技术

针对传统数字正交变换存在A/D采样速率要求比较高导致后续的数字低通滤渡成为瓶颈、运算数据量大、需要正交本振等方面的不足,提出了一种基于软件无线电多相滤波的数字正交变换技术.首先分析基于多相滤波的数字正交变换的实现理论,实现模型,然后设计由于奇偶抽取引起的多相滤波器中的两个延时滤波器,最后在MATLAB/SIMULINK下建模仿真.实验仿真结果表明,用该方法设计的正交变换满足要求.     

基于多相滤波的PCM/FM正交解调

传统的相干正交解调方法,需要提取同频同相的载波,从而增加了解调的难度。根据遥测系统脉冲编码调制/调频（PCM/FM,Pulse Code Modulation-Frequency Modulation）信号的特点,采用基于多相滤波的解调方法。该方法通过多相滤波的方式来实现正交变换,不需要在接收端恢复同频同相的载波,从而降低了传统解调方法中电路实现的难度。通过MATLAB对信号进行调制解调的仿真,比较了不同解调方法对信号的解调效果,并在表格中显示了解调的误码率数据,从而验证了该方法的可行性和优越性。     

一种多模式合成孔径雷达数字接收机

针对一种多模式极化合成孔径雷达（SAR），给出了中频数字接收机工作参数选择，混频滤波方法，实现了三种带宽信号的数字正交解调。通过分析同相、正交通道误差对正交解调性能的影响，确定了滤波器最佳设计准则。最后给出了基于FPGA的实现结构，仿真试验结果表明中频数字接收机性能比一般模拟接收机有显著提高。     

一种简单的直接数字正交变换技术

为了尽可能多地用软件来实现通信接收机的处理功能，需要直接对中频信号进行采样，然后通过数字正交变换的方法得到同相和正交分量。首先对基于多相滤波法的数字正交变换原理进行分析，然后根据多抽样率信号处理理论，详细证明了内插时延滤波器能够用多相滤波器组中的子滤波器实现。     

相位敏感光时域反射系统数字正交解调算法分析及改进研究

对相位敏感光时域反射系统数字正交解调算法进行了研究。分析了正交解调算法中数字滤波器群延时对系统定位精度的影响,提出采用重定位方法矫正定位误差;同时,研究了系统空间分辨率受正交解调算法中数字滤波器的影响,并通过仿真和实验,验证并分析了上述问题。结果表明,重定位方法可消除正交解调算法中数字滤波器造成的定位误差,系统空间分辨率由系统结构与数字滤波器共同决定,且由数字滤波器决定的空间分辨率随数字滤波器阶数的增加而增加。实验中解调选择112阶滤波器较佳。     

宽带数字接收机I/Q幅相不一致性的校正

随着数字技术的发展,正交双通道变换在接收机中得到了广泛的应用。但是,由于各种因素的影响,I／Q通道的正交一致性并不能得到完全的保证,这会降低接收机的动态范围,进而影响接收机的性能。本文提出了一种宽带数字接收机I／Q幅相不一致性的校正方法,首先通过一种时域方法获得误差信息,接着构造滤波器组对I／Q信号进行校正。仿真结果表明,这种方法能有效提高宽带接收机I／Q通道的正交一致性。     

基于多相滤波原理的数字正交采样技术

针对传统正交采样方法存在运算数据量大,镜频抑制比小及硬件实现资源消耗大等方面的不足,分析了一种基于多相滤波结构的数字正交采样方法.首先对多相滤波法实现数字正交变换的原理进行了分析,然后根据多速率信号处理理论推导并给出了基于多相滤波结构的子滤波器的实现方法,最后,通过仿真验证了该方法的有效性.实验结果表明该方法较之传统的低通滤波法有很大的优越性.     

多相滤波的数字相干检波原理及FPGA实现

多相滤波是实现数字下变频及数字相干检波的关键技术,是雷达、声纳和通信等系统中为数字信号处理提供高质量的正交信号的有效手段。文中讨论了多相滤波的基本原理,给出了采用多相滤波的方法对中频带限信号处理的仿真分析,并结合一款脉冲压缩雷达中频数字化接收机的实现方案进行工程验证,结果表明,在技术指标上可有效克服正交通道不一致问题,具有较高的应用价值。     

基于多相滤波法的中频信号正交解调的CPLD实现

正交相干检波可以将复包络的所有信息进行保留,所以在数字信号处理中得到广泛应用。该文讨论了数字信号正交相干检波的多相滤波实现方法,并且给出了基于 CPLD 的 IC 实现。计算机仿真结果表明,多相滤波方法可以提高信噪比,实现高性能数字信号处理的要求。     

Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation

The polyphase filter approach to quadrature demodulation is shown to be well suited for the implementation of purpose-designed wide bandwidth digital quadrature demodulators. The duplicated polyphase filter approach is introduced, as a way to increase the maximum allowable input signal bandwidth for a given implementation technology. Other algorithmic and architectural considerations specifically applicable to the realization of digital filters in low-cost Field-Programmable Gate Array (FPGA) technology are discussed. A design example suitable for processing input signals centered on an intermediate frequency of 160 MHz with a bandwidth of 45 MHz is presented. This design occupies 83% of the Configurable Logic Blocks (CLBs) in a low-cost Xilinx X4010E-3 FPGA. Additional techniques for further performance optimization are presented.     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

Multirate digital filters, filter banks, polyphase networks, andapplications: a tutorial

The basic concepts and building blocks in multirate digital signal processing (DSP), including the digital polyphase representation, are reviewed. Recent progress, as reported by several authors in this area, is discussed. Several applications are described, including subband coding of waveforms, voice privacy systems, integral and fractional sampling rate conversion (such as in digital audio), digital crossover networks, and multirate coding of narrowband filter coefficients. The M-band quadrature mirror filter (QMF) bank is discussed in considerable detail, including an analysis of various errors and imperfections. Recent techniques for perfect signal reconstruction in such systems are reviewed. The connection between QMF banks and other related topics, such as block digital filtering and periodically time-varying systems, is examined in a pseudo-circulant-matrix framework. Unconventional applications of the polyphase concept are discussed     

基于多相滤波的ILS信号的数字正交变换技术

为了尽可能多地用软件来实现仪表着陆系统（ILS）接收机的信号处理,需要对导航信号进行数字化,而基于多相滤波的数字正交变换无需正交本振,结构上也更适用于实时处理系统。介绍了ILS的工作原理及信号体制,研究了基于多相滤波的ILS信号的数字正交变换技术,通过MATLAB仿真验证了设计的可行性。     

基于FPGA的数字化正交解调接收机最优设计

结合抽取滤波器的多项滤波结构,在一定条件下,推导出了一种含抽取正交解调接收机最优结构设计方法。在FPGA乘法器资源相同的条件下,采用最优结构设计的接收机内部FIR滤波器阶数比直接实现形式高了近4倍。最后给出了设计实例。     

Analysis of a high frequency and wide bandwidth active polyphase filter based on CMOS inverters

An active polyphase filter capable of high frequency quadrature signal generation has been analyzed. The resistors of the classical passive polyphase filter have been replaced by transconductors, CMOS inverters (F. Tillman and H. Sjöland, Proceedings of the Norchip Conference (pp. 12–15), Nov. 2005; Analog Integrated Circuits and Signal Processing, 50(1) 7–12, 2007). A three-stage 0.13 μm CMOS active polyphase filter has been designed. Simulations with a differential input signal show a quadrature error less than 1° for the full stable input voltage range for frequencies from 6 GHz to 14 GHz. Phase errors in the differential input signal are suppressed at least three times at the output. Corner simulations at 10 GHz show a maximum phase error of 3° with both n- and pMOS slow, in all other cases the error is less than 0.75°. The three-stage filter consumes 34 mA from a 1.2 V supply. To investigate the robustness of the filter to changes in inverter delay, an inverter model was implemented in Verilog-A. Linear c _in and g _in were used, whereas g _m , c _out , and g _out were non-linear. It was found that the filter could tolerate substantial delays. Up to 40° phase shift resulted in less than 1.5° quadrature phase error at the output.