基于地址映射的NAND Flash控制器设计

针对嵌入式数据采集系统对NAND Flash进行读写控制时出现的坏块问题和磨损失衡问题,对数据采集系统的工作特点进行分析,借鉴闪存转换层的思想,提出了一种基于地址映射的NAND Flash控制方法,通过建立、维护、查询NAND Flash存储块逻辑地址与物理地址之间的映射关系表,实现NAND Flash的坏块管理和磨损均衡功能,同时介绍了使用地址映射方法的NAND Flash控制器设计过程;仿真测试和实际应用结果表明,基于地址映射方法设计的NAND Flash控制器能够识别、管理出厂坏块和突发坏块,均衡存储块的磨损,提高嵌入式数据采集系统的可靠性;该方法实现过程简单,无需移植文件系统,硬件资源要求低,为嵌入式数据采集系统中NAND Flash的读写控制提供了新的思路。     

YAFFS嵌入式文件系统应用研究

本文介绍了NAND闪存设备的特点和针对NAND闪存设计的YAFFS（Yet Another Flash File System）嵌入式文件系统,并且详细探讨了在ARM处理器3SC2410和嵌入式Linux平台上建立基于NAND闪存的YAFFS根文件系统的方法步骤,同时给出了详细的代码。     

U-Boot在s3c2410上的移植及功能扩展

考虑到Bootloader在嵌入式系统开发及产品升级方面的重要性及近年来NAND Flash闪存在嵌入式系统应用中的广泛性,提出了U-Boot从NAND Flash闪存设备启动的方法.详细地介绍了U-Boot源码结构及其启动流程,并分析了NAND Flash闪存工作原理及操作方法,实现了U-Boot从NAND Flash闪存启动以及U-Boot以命令行形式操作NAND Flash的功能.最后,实验结果表明了U-Boot在s3c2410处理器上成功的移植.     

基于USB2.0总线的NAND Flash检测及控制方法

在高速大容量存储装置设计中多采用NAND Flash存储器,针对目前采用串口检测坏块、实现数据读写的方法存在检测速度慢、等待时间长等缺点,提出了基于USB2.0总线的NAND Flash检测与控制方法。利用FPGA逻辑控制功能和高速USB接口芯片设计通信和控制电路,并通过上位机软件实现对Flash的命令、操作控制,由用户通过PC应用程序完成对NAND Flash的读写、擦除检测及坏块标定。经实验应用验证,该方法检测、读写速度快,使用灵活,能准确、有效实现数据的快速读写、擦除及坏块标定,可广泛应用于存储测试装置的设计研制中。     

非易失存储器NAND Flash及其在嵌入式系统中的应用

文中介绍了NAND Flash的芯片内部组织结构、主要的外部引脚及其功能、NAND Flash的类型、NAND Flash所支持的文件系统、与微处理器的连接和NAND Flash的固有特性,并对比了NAND和NOR Flash的异同。最后简述了闪存固件程序架构和如何在Linux操作系统中加入对NAND Flash的支持。     

非易失存储器NAND Flash及其在嵌入式系统中的应用

文中介绍了NAND Flash的芯片内部组织结构、主要的外部引脚及其功能、NAND Flash的类型、NAND Flash所支持的文件系统、与微处理器的连接和NAND Flash的固有特性，并对比了NAND和NAND Flash的异同。最后简述了闪存固件程序架构和如何在Linux操作系统中加入对NAND Flash的支持。     

基于NAND Flash的转译层的设计

基于NAND Flash的嵌入式存储系统以其轻巧便携、读写速度快等特点成为当前嵌入式存储系统的主流配置.但由于固有坏块以及在擦、写过程中随机产生的坏块影响了NAND Flash的实际应用,所设计的NAND Flash的驱动转译层具有坏块管理机制并实现上层文件系统的连续读写功能.     

高性能NAND Flash控制器在SoC平台中的设计与应用

NAND Flash在现代数码产品中得到了广泛的应用,在片上系统芯片中集成NAND Flash控制器已成为一种趋势。分析SoC平台中高性能NAND Flash控制器的实现方案,提出两种改进NAND Flash控制器数据读写速度的技术,在面积增加很小的情况下,有效地改善了控制器的性能。该设计方法已通过了仿真测试和FGPA验证,在SMIC 0.18μm工艺库下的综合速度能够达到121MHz。     

NAND闪存存储文件系统

NAND闪存已经成为便携式设备的主要存储介质。由于闪存自身的物理特性,需要在现有文件系统层与闪存的存储物理层之间引入闪存转换层。但是,现有文件系统主要针对磁盘存储系统设计的,没有考虑NAND闪存物理特性。这种方法效率低、影响便携式设备的性能。本文概述了NAND闪存的存储文件系统,分析比较了其中三种主要文件系统,为基于NAND闪存存储介质的便携式系统设计提供了参考意见。     

基于4KB数据块映射的固态硬盘算法

固态硬盘(Solid-State Drive,SSD)采用NAND型闪存(Flash Memory)为主要存储介质,闪存的读写不同于其他介质,需要闪存转换层(Flash Translation Layer,FTL)对闪存的存储空间进行管理。传统方式的映射算法随着页面(Pagesize)的逐渐扩大,在随机数据块写入的速度方面难以提升。针对这个问题,提出一种基于4KB数据块映射的闪存转换层算法,固态硬盘控制器芯片采用110nm工艺实现,集成了SATA-Ⅱ接口(3Gb/s数据传输速率),最大可以并行驱动5通道的闪存芯片。该算法结合芯片的内部资源,经过了可靠性检测,达到了预期的可靠性和读写速度。     

基于NAND Flash的CPU安全启动设计与实现

NAND Flash存储器以其容量大、成本低和速度快的优势,在嵌入式系统中得到广泛的应用。但是,由于NAND Flash固有的器件特性,必须要有驱动才能对其进行读写,存储于其上的代码不能直接执行,因此其并不适合作为系统启动代码的存储介质。一般采用NOR Flash存储启动代码并直接执行,然后再引导存储于NAND Flash中的操作系统镜像,这增大了系统成本和功耗。设计并实现了一种基于NAND Flash的CPU安全启动方法。该方法首先通过软硬件结合的方式,在片内NAND Flash控制器中增加块映射表结构,并由NAND Flash中第1块空间存储的代码进行好块寻找和块映射表填写,使NAND Flash的一部分存储空间可以直接映射为硬件可访问的内存空间,从而使得NAND Flash可以作为系统启动的存储介质,实现仅需NAND Flash存储的系统。还提出了一种扩展BootROM的方案,结合NAND Flash地址映射结构,将片内BootROM的一部分扩展到NAND Flash的第1块存储空间中,并通过Hash比对验证BootROM,从而有效降低了片内BootROM的设计复杂度,减少了代码量。通过提出的方法,可以有效地实现单NAND Flash系统的安全启动,降低了系统成本,提高了系统的安全特性。     

Real-time emulation and analysis of multiple NAND flash channels in solid-state storage device

NAND Flash is the most prevalent memory technology used today in data storage systems covering a wide range of applications, from consumer devices to high-end enterprise systems. In this work, we present a modular and versatile FPGA-based platform that achieves accurate emulation of multiple NAND Flash channels. The NAND Flash emulator is based on an expandable and reconfigurable architecture that can be used for developing and testing new NAND Flash controllers and for analysing the behaviour of existing NAND Flash controllers and/or host device drivers. The presented NAND Flash emulator is based on PCIe-based FPGA boards attached to a high-end server, supports standard memory interfaces, responds to all memory commands in proper time and has the capability to emulate memory space in the range of a few TBs. The NAND Flash emulator has been prototyped and tested, and experimental results demonstrate that all timing requirements are satisfied under maximum read/write workloads. The NAND Flash emulator also includes a hardware tracer unit that records information of all commands exchanged at the NAND Flash interfaces along with high resolution timestamps. The recorded information can be used to analyse higher level functions, like wear leveling and garbage collection, and combined with other software tools for analysing cognitive functions. Experimental results demonstrate the advantage of using this emulator for analysing how host device drivers implement wear leveling and garbage collection functions.     

嵌入式平台S3C6410的U-Boot分析与移植

详细分析基于S3C6410的嵌入式平台的U-Boot源代码和启动过程.在此基础上成功移植了U-Boot软件,实现了S3C6410处理器时钟初始化、串口通信、内存初始化、MMU初始化、NAND Flash初始化.通过移植NAND Flash驱动,实现读写NAND Flash和从NAND Flash启动的功能,使得整个系统能够正常运行.     

一种混合映射闪存转换层的设计与实现

使用NAND Flash作为存储媒介的存储设备常需要闪存转换层(FTL)对NAND进行管理。页映射是一种常见的映射方式,但需要很大的内存存放页映射表,在嵌入式环境下这一条件往往无法满足。针对该问题,提出一种基于超级块的混合映射FTL,包括坏块管理、地址翻译、垃圾回收、上电恢复,使用的SRAM空间不到128 KB,远小于页映射,同时不需要存储映射表,程序在固态硬盘开发板上成功运行,实现固态硬盘基本读写功能。测试结果表明,该混合映射FTL方案具有较好的顺序读写性能。     

支持ONFI和Toggle模式的NAND Flash PHY设计

论文设计了一种能支持ONFI2．1与Toggle1．0模式的NAND Flash PHY,完成了其读写通道、地址与控制逻辑的设计,并采用读门控电路消除DQS读前后的毛刺。功能仿真与静态时序分析结果表明,PHY的设计达到了ONFI与Toggle标准时序要求。NAND Flash PHY面积为45245．5μm^2,动态功耗为1．16mW,静态功耗为95．8μW。     

基于STM32的Flash存储器坏块自动检测

针对Nand Flash存储器存在坏块的问题, 提出一种基于STM32的Flash存储器坏块自动检测方法, 通过STM32内部可变静态存储控制器, 发出相应的数据、地址、控制信号, 在不增加外部器件的情况下, 快速访问Flash存储器, 并给出了部分硬件电路和C语言编写的程序代码. 该设计已成功实现自动检测Flash坏块的功能; 操作简单、检测速度快、准确率高; 并能读取Flash的ID号检测Flash性能, 同时能够存储和读取2GB数据.     

YAFFS文件系统的研究与改进

通过对NAND Flash硬件特点和YAFFS文件系统的分析与研究,在遵循NAND Flash“只写一次”限制的基础上,提出改进删除页操作的新策略,给出改进的实现过程,重点涉及实现中的难点及相应的解决策略。在一款龙芯开发板上的测试表明,该改进策略能够把改写、删除和截短文件等文件系统基础操作的性能提高约40%,具有很高的实用价值。     

Cascaded Write Amplification of LSM-tree-based Key-Value Stores underlying Solid-State Disks

Log-structured merge tree (i.e., LSM-tree)-based key–value stores (i.e., KV stores) are widely used in big-data applications and provide high performance. NAND Flash-based Solid-state disks (i.e., SSDs) have become a popular storage device alternative to hard disk drives (i.e., HDDs) because of their high performance and low power consumption. LSM-tree KV stores with SSDs are deployed in large-scale storage systems, which aims to achieve high performance in the cloud. Write amplification in LSM-tree KV stores and NAND Flash memory in SSDs are defined as WA1 and WA2 in this paper. The former, which is attributed to compaction operations in LSM-tree-based KV stores, is a burden on I/O bandwidth between the host and the device. The latter, which results from out-place updates in NAND Flash memory, blocks user I/O requests between the host and NAND Flash memory, thereby degrading the SSD performance. Write amplification impairs the overall system performance. In this study, we explored the two-level cascaded write amplification in LSM-tree KV stores with SSDs. The cascaded write amplification is represented as WA. Our primary goal is to comprehensively study two-level cascaded write amplification on the host-side LSM-tree KV stores and the device-side SSDs. We quantitatively analyze the impact of two-level write amplification on overall performance. The cascaded write amplification is 16.44 (WA1 is 16.55; WA2 is 0.99) and 35.51 (WA1 is 16.6; WA2 is 2.14) for SSD-I and SSD-S with LevelDB’s default setting under DB_bench. The larger cascaded write amplification of KV stores has a bad impact on SSD performance and lifetime. The throughput of SSD-S and SSD-I under an 80%-write workload is approximately 0.28x and 0.31x of that under a 100%-write workload. Therefore, it is important to design a novel approach to balance the cost of an SSD lifetime caused by cascaded write amplification and its high performance under the read-write-mixed workloads. We attempt to reveal details of cascaded write amplification and hope that this study is useful for developers of LSM-tree-based KV stores and SSD software stacks.     

Next high performance and low power flash memory package structure

In general, NAND flash memory has advantages in low power consumption, storage capacity, and fast erase/write performance in contrast to NOR flash. But, main drawback of the NAND flash memory is the slow access time for random read operations. Therefore, we proposed the new NAND flash memory package for overcoming this major drawback. We present a high performance and low power NAND flash memory system with a dual cache memory. The proposed NAND flash package consists of two parts, i.e., an NAND flash memory module, and a dual cache module. The new NAND flash memory system can achieve dramatically higher performance and lower power consumption compared with any conventionM NAND-type flash memory module. Our results show that the proposed system can reduce about 78% of write operations into the flash memory cell and about 70% of read operations from the flash memory cell by using only additional 3KB cache space. This value represents high potential to achieve low power consumption and high performance gain.     

大容量NAND Flash文件系统转换层优化设计

针对基于NAND Flash转换层(NFTL)架构的Flash文件系统在大容量NAND Flash设备上存在的性能不足,本文分析了NFTL的存储管理机制,基于vxworks嵌入式系统平台提出了对NFTL模块的优化设计方法并进行了具体实现。实验表明,优化后的NFTL模块有效提高了文件系统的读写性能,缩短了加载时间。