基于全耗尽技术的SOI CMOS集成电路研究

介绍了电路的工作原理，对主要的延迟和选通控制单元及整体电路进行了模拟仿真，证明电路逻辑功能达到设计要求。根据电路的性能特点，采用绝缘体上硅结构，选用薄膜全耗尽SOICMOS工艺进行试制。测试结果表明：与同类体硅电路相比，工作频率提高三倍，静态功耗仅为体硅电路的10％，且电路的101级环振总延迟时问也仅为体硅电路的20％，实现了电路对高速低功耗的要求。     

整数阶电路定理到分数阶电路推广及分析

近几十年来，对分数阶电路的研究逐渐深入，但对其中电路定理的分析较少，因此针对分数阶电路需要进一步探究其规律，将一些经典的电路定理推广到分数阶电路中，使得在以后的分析过程中能直接使用。在整数阶电路定理的基础上，运用基尔霍夫定律在分数阶电路中证明了叠加定理、替代定理、等效电源定理和互易定理，并进行了应用分析。     

基于Smith圆图的射频功放电路的设计与分析

基于Smith圆图设计射频匹配电路，提出了大功率射频放大电路的设计方法，采用MRF9060芯片，运用如Pspice和ADS等开发软件，实现了包括直流偏置电路、保护电路、匹配滤波电路以及射频放大电路在内的整体设计，并给出了对系统增益、回波损耗等指标的仿真结果。     

基于离散傅里叶变换的光纤陀螺电路串扰自检测

光纤陀螺由于构造限制，电路输出信号中易受驱动信号串扰，导致输出结果精度难以满足现实需求，影响了电路工作的安全性和效率。为此，提出基于离散傅里叶变换的光纤陀螺电路串扰自检测方法。首先，分析光纤陀螺电路串扰的原理，对光纤陀螺电路进行闭环检测，获取到电路信号变化规律。其次，根据得到的干扰信号函数，建立电路串扰模型，由于电路串扰间存在互容特性，针对串扰线路使用基尔霍夫电压定律，结合电流的连续性，建立串扰电路信号变化函数；根据光纤陀螺检测中的振动频率，依据电路串扰的时间序列以及电路零均值、非高斯、统计非零峰度，使用离散傅里叶变换解析串扰信号，完成电路串扰的自动检测。经实验验证：本文方法能够节省大量提取时间，平均耗时节省35min，检测精度提高34%，能高效的完成串扰检测。     

RISC-V指令集子集RV32I的译码电路设计与优化

面向RISC-V处理器五级流水线数据通路，设计了基于FPGA的RISC-V指令集子集RV32I的指令译码电路。电路分为主译码电路和程序计数器输入选择(PCSel)译码电路，使用Verilog HDL编程设计，并进行了系列优化:使用时序约束工具分析时序状态，设定约束后对电路进行综合，降低电路延迟;利用无关项化简组合逻辑，减少模块输入输出项，减少电路级联;构建独立的32位串并行数值比较器;插入流水线，提高电路工作频率。电路基于FPGA芯片CycloneⅣEP4CE6F17C6进行设计，使用Quartus Prime 17.1对电路进行仿真，仿真结果表明:在Slow 1 200 m V 85℃条件下，指令译码电路达到295.6 MHz的工作频率，相比同类设计具有高速和低资源消耗的特点。     

单片集成MEMS电容式压力传感器接口电路设计

介绍了一种单片集成电容式压力传感器接口电路，该电路基于电容一频率转化原理，并通过差频消除了温度变化和工艺波动对电路性能的影响。使用Pspice对接口电路的误差特性进行了分析，并依据仿真结果确定了电路的相关参数。最后给出电路的测试结果，测试结果与仿真结果一致，在80～110kPa量程内，接口电路的分辨率为3．77Hz／hPa。     

基于有效布尔矩阵的线性最近邻量子电路综合?

量子电路要求满足最近邻约束，只允许在相邻的量子位之间交互，线性量子电路是量子电路的一个重要部分。研究了表示线性最近邻量子电路的布尔矩阵有效性的快速判定方法，时间复杂度从n!(n-1)变为O(n2)。提出了基于有效布尔矩阵的大规模线性最近邻量子电路的并行综合算法，对128线的任意线性最近邻量子电路在不到10 s内完成了电路综合。提出的并行方法不仅保证了精度，也大大减少了量子电路的综合时间，扩大了求解电路的规模。     

集成电路抗腐蚀能力的研究

首先介绍了塑封电路、玻璃封装电路和陶封电路的构成材料，然后分别选取这3种电路的若干只样品，按几种试验条件进行了盐雾试验，针对试验后在电路上出现的腐蚀现象进行了理论分析，最后总结了3种电路各自的抗腐蚀能力。     

基于分布式海量电力数据处理方法的设计

针对现有技术电力数据计量检定存在的技术弊端，该研究采用具有多路接口的CS5464芯片，该电路包括放大器电路、调制电路、数字滤波电路和数据通讯电路。在计算电力数据量时，采用16位MSP430FG4619的MCU内核计算电路，包括运算器电路、控制器电路、存储器电路、输入输出设备构成。在进行电力信息计量数据管理时，采用改进最大最小蚁群算法(Min Max Ant System, MMAS),并融合分类算法模型，能够对多种电力信息计量数据信息进行信息分类，提高了电力数据计量检定信息管理能力。通过试验，该研究的方法误差率较低，稳定度较高。     

基于单端正激变换的地线取电系统电源电路仿真设计

为解决输配电系统检测设备供电难题，设计了能够从输电线路架空地线取电系统电源电路，根据输电线路地线感应电压不稳定的特点，采用不可控整流桥和单端正激变换电路，结合闭环控制技术，设计并搭建了电路模型，通过分析在不同输入电压情况下电路的输出特性，验证了电路可行性，该电源电路实现了将9Ｖ~ 100Ｖ 可变交流输入转换为12Ｖ 稳定直流输出，并且通过拟合不同负载情况下电路输出功率特性曲线，分析得出电源电路输出功率稳定。     

基于比特平面的快速中值滤波器设计与实现

提出基于比特平面的快速中值滤波算法硬件实现结构和核心处理电路,在减少了中值滤波电路面积的情况下,显著提高了处理速度.提出的比特平面算法硬件实现结构的面积与滤波数据长度和量化比特教成近似线性关系,适于各种滤波窗口大小和数据精度的中值滤波;算法硬件实现结构规则,特别适于用FPGA实现.     

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent corner error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 m CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.     

一种用于GSM系统的多层平面有源滤波器

给出一种新颖可用于GSM系统手持机(MS)的甚小型多层平面有源滤波器的结构、等效电路模型、最优化的数学模型和实现方法。提出了提高程序运行效率的“优化筛选法”。计算并讨论了1.85GHz频率下该滤波器的结构参数值和等效电路元件值与射频参数的关系,由此获得了最佳结构参数和等效电路值,计算表明在通带范围内该滤波器具有低噪声性能。     

A review of median filter systems for analog signal processing

This paper presents a review of existing analog implementations of the median and other ranked-order filter operations. The basic properties of median signal processing are first reviewed. Different analog median filter architectural approaches and implementations, introduced by several authors, are then discussed. These include filters based on analog delay lines and either nonlinear selection networks or ramp voltage generators. The Linear-Median Hybrid filter concept is presented and two examples of analog circuit implementations are given. Finally, a neural network approach is discussed.     

Design rules for an integratable low-power amplifier/filter combination

In this paper design rules for a circuit topology in which there is an inseparable combination of an amplifier and a filter characteristic, are presented. By intentionally using the capacitance of an already present input sensor for the filtering, the total required integrated capacitance is much less than that in circuits, which have a separately designed amplifier and filter function. Consequently, it is possible to have the advantage of a better integratability. Moreover, less complexity in the design is achieved. The presented circuit shows a current-to-voltage conversion and an inherently controllable second-order low-pass filter characteristic. A discrete realization has been designed to test the circuit. This circuit operates down to a 1 V supply voltage and the transfer shows a 1.8 M currentto-voltage conversion with a bandwidth of 6 kHz. Measurement results of this circuit show that a 63 dB dynamic range can be achieved with a total required integrated capacitance of only 31 pF.     

高带外抑制声表面波扇形滤波器的研制

根据混合场等效电路模型,详细分析了抽指加权结构对扇形又指换能滤波器频响的影响。在考虑了指间反射、三次行程以及指条寄生阻抗等情况下,根据扇形换能器的导纳矩阵及其外围电路参数得到器件总的频率响应,并通过改变发射和接收换能器指对数来改善扇形又指换能滤波器带外抑制。     

Analogue median/average image filter based on cellular neuralnetwork paradigm

A cellular neural network-based image filter is presented, which alloys for median and mean image filtering. The circuit implements an array of 3×64 analogue processing elements (cells) and appropriate additional circuitry. Images are loaded into the circuit, are read out of the circuit serially, and are processed in real-time     

Passive and Active Hybrid Integrated EMI Filters

Two new planar integrated electromagnetic interference (EMI) filter structures that reduce the filter volume and that are based on standard printed circuit board (PCB) process technology are presented in this paper. First, a passive integrated EMI filter is presented, which results in a volume reduction of 24% compared to the discrete solution. However, this filter requires a planar ferrite core for the common-mode inductor. In order to eliminate the ferrite core and reduce the filter volume further ($-$ 40% versus discrete filter), a passive integrated structure is combined with an active EMI filtering circuit. The transfer function, the volume, and the losses of the discrete and the two integrated filters, which are designed for a 600 W power-factor-corrected converter, are compared.      

Synthesis of Log-Domain Filters from First-Order Building Blocks

Log-domain filters are an important class of current-mode circuits having large-signal linearity and increased tuning range over voltage-mode filter circuits of similar complexity. In this paper we describe synthesis of a single-ended, first-order filter circuit from static and dynamic translinear circuit principles, and show how higher-order filters can be easily constructed from the first-order building block. We address additional issues related to low-frequency (audio-frequency) filter design and present results measured from test circuits and a complete 15-channel filterbank system fabricated in 2 m and 1.2 m BiCMOS processes.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.