在总线型局域网中如何提高线路利用率

一、提高线络利用率的途径目前在计算机局域网中常用的拓朴结构有环型和总线型两种,其中总线型用的甚多这是因为总线型网络结构简单,节点的增加或删除比较方便,总线网络的信道访问控制方式CSMA/CD和Token Bus比较成熟的     

基于软总线的开放式数控系统软件结构的研究

本文遵循开放式数控系统软件结构要求,提出了一种基于软总线的开放式数控系统结构,系统的功能单元采用模块化设计,并统一了的模块内部基本结构,同时功能模块之间利用标准化的软总线进行通讯,由此形成了一个多层次,局部自治的总线型系统结构,实现系统功能的可配置、可扩展、可重构.     

烟草制丝线PROFIBUS现场总线拓扑结构的改进

目前烟草行业普遍使用的PROFIBUS现场总线,一般都是采用线型总线拓扑结构,很少采用线型或树型的混合型总线拓扑结构。使用先进的网络组件ProfiHub和COMbricks,可以实现线型/树型的混合型总线拓扑结构。主要从PROFIBUS现场总线的拓扑结构、故障特点和排除方法等方面进行比较,突出混合型总线拓扑结构相对于线型总线拓扑结构具有的优势,以制丝线某工艺段为例,介绍改进前后的实际效果。     

总线型阀岛在电厂化水程控中的应用

针对机电一体化的总线式阀岛的特点,采用对比法比较了常规的控制方案与应用总线型阀岛控制方案两者之间的差别。结果表明,总线式阀岛使得电控阀的布线容易,简化了系统的调试和性能的检测、诊断及维护工作。总线型阀岛的技术可以应用于电厂,对推广总线式阀岛在电厂的应用具有重要的现实意义。     

总线型交换集线器系统的设计与实现

高速交换技术是高速网络发展的核心和关键技术,该文主要针对基于高性能PCI总线背板的交换结构,系统地论述总线型交换集线器系统的设计与实现。     

自动化仓库管理与控制系统集成设计与实现

分析了自动化仓库管理与设备控制系统的功能需求，指出了它与过程监控系统的不同点，划分了自动化仓库管理与控制系统功能模块。结合以太网和现场总线的技术特点，设计了以交换式快速以太网为主干、以总线型现场总线为底层的系统集成网络结构，给出了基于以太网的设备监控通信协议分层模型。通过介绍该设计在某企业生产仓储兼有物流功能的自动化仓库的实现，阐明了仓库管理与监控系统软件的集成。该设计使用通用器件和通用技术以较低成本实现了自动化仓库管理与控制系统集成，具有易于扩展和维护的优点。     

总线型分布式计算机系统DMCOSⅡ

本文描述了一个总线型分布式计算机系统DMCOSⅡ。DMCOSⅡ的最大特点是在总线式结构中引入了环式结构中的“控制标志”概念,采用了控制标志法做为它的网络控制方法。经分析知道,对于机器数量不太多的总线型分布式计算机系统来说,采用控制标志方法比采用其他网络控制方法好些。 第一节描述了DMCOSⅡ的概貌,第二和第三节分别描述了系统的硬件和软件结构,最后一节分析了系统的一些特点。     

基于CAN总线磁悬浮球系统分布式控制设计与实现

选用国际上应用最广泛的现场总线之一—CAN总线,对磁悬浮球控制系统进行分布式控制,设计并实现了CAN总线磁悬浮球控制系统。首先,对磁悬浮球控制系统进行了详细分析,确定了系统的总线型网络拓扑结构。在该网络结构下,进行软硬件设计。硬件设计工作主要是设计一个通用CAN节点的设计,使其能够完成模拟量的精确快速采样、高精度输出以及开关量的控制三大功能。软件设计包括两部分:CAN节点中基于ARM的软件设计和PC端监控软件的设计。     

基于485总线分布式监控系统的研究与实现

结合现场总线的应用,将RS485总线的物理信号和基金会现场总线的通讯协议进行融合,制定出一种可靠性高、实时性好且成本及维护费用低的通讯控制系统,从而给出了一种总线型分布式监控系统的实现方案。该方案在供水监控领域得到了广泛应用。     

基于485总线分布式监控系统的研究与实现

结合现场总线的应用,将RS485总线的物理信号和基金会现场总线的通讯协议进行融合,制定出一种可靠性高、实时性好且成本及维护费用低的通讯控制系统,从而给出了一种总线型分布式监控系统的实现方案.该方案在供水监控领域得到了广泛应用.     

基于CAN总线的自动测控系统

介绍了基于CAN总线的自动测控系统基本组成和具体实现,给出了虚拟仪器软件简图。CAN总线的自动测控系统以其设计简单、可靠性高、可维护性好和操作性强等优点,将有很大发展。     

基于总线的多DSP交叉调试器的设计与实现

探讨了在使用总线与主机连接的多DSP系统上构建交叉调试器的方法，分析了在多DSP系统中使用硬件仿真器进行调试的不足，讨论了在DSP上实现软件调试器的基本原理。针对DSP资源有限的特点，提出了动态monitor的方式降低调试器对DSP的资源占用。测试和使用表明，与硬件仿真器相比，基于总线的软件调试器具有更好的性能、更高的性价比以及更好的多处理器支持。     

On the Power of Segmenting and Fusing Buses

Reconfigurable bus-based models of parallel computation have been shown to be extremely powerful, capable of solving several problems in constant time that require nonconstant time on conventional models such as the PRAM. The primary source of the power of reconfigurable bus-based models is their ability to dynamically alter the connections between processors by manipulating the communication medium. This can be viewed as the models' ability to (i) segment a bus into two or more bus segments and (ii) fuse two or more buses or bus segments together. In this paper, we investigate the contribution of the abilities of a reconfigurable bus-based model to segment and fuse buses. We show that the ability to fuse buses is the more crucial of the two. The ability to segment buses enhances the power of the model under certain circumstances. We also study the roles of concurrent reading and writing in the context of reconfigurable bus-based models. These results establish a hierarchy of powers of the PRAM and reconfigurable bus-based models.     

一种基于CAN总线的电力参数监测系统

介绍了一种基于CAN总线的电力参数监测系统的硬件和软件设计方案。以自带CAN总线控制器的ARM处理器LM3S2016为核心,利用其片上外设完成电压、电流和频率的采集和实时传输。采用隔离型CAN总线驱动器CTM8250T,避免了用分立;元件实现,使得设计简单、结构紧凑。     

采用C/S结构的遥测数据处理系统及其实现技术

简要介绍了采用C／S结构的遥测数据处理系统的组成和体系结构,较为详细地介绍了其中的关键设备——基于cPCI总线的遥测前端处理器的硬件选择和软件设计,并对系统中的管理服务器、显示工作站的功能及相关软件给予了简述。     

Bus-based park-and-ride system: a stochastic model on multimodal network with congestion pricing schemes

This paper focuses on modelling the network flow equilibrium problem on a multimodal transport network with bus-based park-and-ride (P&R) system and congestion pricing charges. The multimodal network has three travel modes: auto mode, transit mode and P&R mode. A continuously distributed value-of-time is assumed to convert toll charges and transit fares to time unit, and the users’ route choice behaviour is assumed to follow the probit-based stochastic user equilibrium principle with elastic demand. These two assumptions have caused randomness to the users’ generalised travel times on the multimodal network. A comprehensive network framework is first defined for the flow equilibrium problem with consideration of interactions between auto flows and transit (bus) flows. Then, a fixed-point model with unique solution is proposed for the equilibrium flows, which can be solved by a convergent cost averaging method. Finally, the proposed methodology is tested by a network example.     

基于遗传算法的NoC处理单元映射研究

传统的基于总线的SoC体系结构及设计方法在解决多处理器的复杂系统中将遇到瓶颈, 有效解决方案NoC(片上网络)成为新的发展趋势.本文研究了广泛使用的二维规则型网络(2D-mesh)对影响系统性能的重要因素--功耗建立模型,以及形成处理单元位置映射等问题.最后运用遗传算法来寻找已建立的功耗模型最优解或近最优解.试验结果表明,遗传算法能够使得目标函数很快收敛,起到了很好的全局寻优效果.     

VXI总线高速数字图像接收模块设计

在某VXI总线自动测试系统中,为实现被测对象的高速数字图像的接收,设计了VXI总线高速数字图像专用接收模块。在硬件方面,通过电平转换和光电隔离将RS-422A差分电平的数字图像信号转换为标准TTL信号,经过FPGA自动存储在静态RAM中,接收完毕后由DSP将存储的图像数据经过VXI接口传至上位机。在软件方面,设计了上位机面板、驱动程序以及DSP程序,从而实现图像数据的读取与上传。目前该模块已交付使用。     

Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design

Network-on-chip (NoC) is a paradigm shift for communication between cores in multi-processor systems. It has emerged as a solution for addressing the limitations of bus-based communication in multi-processor system design. The use of MPSoC (Multi-Processor System on Chip) based design of real-time safety-critical embedded systems (such as, Avionics, Automotive etc.) is really a challenge because of the requirement of time predictability and reliability of highest degree. Task mapping and flow priority assignment are two crucial steps for real-time NoC design. Most of the earlier work on priority assignment for on-chip communications are either based on exhaustive search or are heuristic in nature.In this paper, a search based explorative solution to the priority assignment problem has been proposed with a Genetic Algorithm (GA) based formulation that uses experimentally determined heuristics to converge faster with a better solution. Unlike other works in the area, proposed work considers the task execution time while assigning flow priorities. The paper proposes a combined priority assignment and task mapping solution. The approach has been validated with two real-time industrial applications - one from automotive domain, while the other one is from avionics.     

Scalable shared-memory multiprocessor architectures

Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures