Testing of Synchronizers in Asynchronous FIFO

This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface.     

Scan Test Response Compaction Combined with Diagnosis Capabilities

As today’s process technologies are combined with ever increasing design sizes, the result is a dramatic increase in the number of scan test vectors that must be applied during manufacturing test. The increased chip complexities, in combination with the smaller feature sizes, require that we now address defect mechanisms that safely could be more or less ignored in earlier technologies. Scan based delay fault testing (AC-scan) enhances defect coverage as it addresses the dynamic behavior of the circuit under test. Unfortunately, the growing number of scan test vectors may in turn result in costly tester reloads and unacceptable test application times. In this paper, we devise a new scan test response compaction scheme based on finite memory compaction (a class of compactors originally proposed in Rajski et al., Convolutional compaction of test responses, 2003). Our scheme is diagnosis friendly, which is important when it comes to maintain throughput on the test floor (Leininger et al., Compression mode diagnosis enables high volume monitoring diagnosis flow, 2005; Stanojevic et al., Enabling yield analysis with X-compact, 2005). Yet, the compactor has comparable performance to other schemes (Mitra et al., X-compact: an efficient response compaction technique, 2004; Mitra S et al., X-tolerant test response compaction, 2005; Rajski et al., Convolutional compaction of test responses, 2003) when it comes to ‘X’ tolerance and aliasing.     

Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction

Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS’89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC’99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits.     

A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)

This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. Specially designed test chips were designed and tested to verify the applicability of the methodology. Simulation studies were also conducted to investigate the effectiveness of the technique. The results presented here clearly establish the significant potential of the proposed new delay testing approach     

基于扫描链的FPGA可编程逻辑模块测试

随着FPGA规模的不断增大和结构的日益复杂,FPGA的测试也变得越来越困难.由此提出了一种可配置的FPGA芯核扫描链设计,并讨论了基于扫描链的可编程逻辑模块（Configuration Logic Blocks CLB）测试.提出的扫描设计可以通过配置调整扫描链的构成,从而能够处理多个寄存器故障,且在有寄存器故障发生时,重新配置后能继续用于芯片的测试.基于扫描链的CLB测试,以扫描链中的寄存器作为CLB测试的可控制点和可观测点,降低了对连线资源的需求,可以对所有的CLB并行测试,在故障测试的过程中实现故障CLB的定位,与其它方法相比,所需配置次数减少50%以上.     

Exploiting distribution of unknown values in test responses to optimize test output compactors

Test output compactors can effectively reduce the data volume of test responses without scarifying fault coverage. However, when there are unknown values (X-bits) in the test output, the fault coverage can be severely comprised. Many compaction schemes that can handle X-bits have been developed. However, existing test response compaction schemes are designed without considering the locations of errors and X-bits. This design methodology essentially assumes that observable errors as well as X-bits are randomly distributed among all scan cells. Recent studies show that X-bits may not be randomly distributed; some scan cells could capture much more X-bits than others. In this paper, we propose to exploit the nonuniform distribution of X-bits to optimize test response compactors such that a higher compression rate is achieved with lower hardware overhead. The proposed design method is applicable to various test output compaction schemes that can handle X-bits in the test responses, including X-blocking, X-masking, and X-tolerant circuits. Experimental results show that, in the presence of X-bits, the compression results will be significantly improved with the help of the proposed method.     

Synthesis of Scan Chains for Netlist Descriptions at RT-Level

This paper presents a methodology to insert scan paths in a functional Register Transfer Level (RTL) specification of a design that can exploit existing functional paths between sequential elements in the original circuit for establishing scan chains. The primary objective for RTL scan insertion is to reduce the time taken for DFT, and thus reduce the time to market. Additionally, building scan chains at the functional RT-Level is expected to reduce the total area overhead introduced by full scan without compromising the fault coverage achieved. In addition, it often eliminates the delay associated with the additional multiplexer as a part of a conventional scan-cell in high performance designs. Experimental results presented in this paper demonstrate that the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.     

Combined probabilistic testability calculation and compact test generation for PLAs

PLAs (programmable logic arrays) may be tested internally by self-test, or externally by applying test patterns. Fault coverage by nonexhaustive self-test is assured by computing a lower bound for estimated fault coverage vs. test pattern number. First, a lower bound for probabilistic detectability per fault is computed by a method based on Shannon's expansion theorem. In the process of finding a lower bound detectability for a particular fault, a test pattern for the fault is generated automatically, at no extra cost. These patterns often contain several don't cares. Traditional test pattern compaction is then applied to the test pattern set. In addition, a novel test pattern compaction method is introduced, suitable for embedded circuitry. The method may be used in conjunction with a serial scan architecture, whereby each test pattern is shifted one position before being applied to the circuit under test. The compaction scheme was applied to a benchmark set of 53 PLAs. An average reduction of 70% in the number of test bits and clock cycles was achieved.¹ This work was done while B. Reppen was with the Norwegian Institute of Technology.     

Efficient Path Delay Testing Using Scan Justification

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip‐flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS’89 benchmark circuits show that the number of testable paths can be increased by about 45% over the conventional functional justification.     

Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs.     

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection

A novel oscillation ring (OR) test scheme and architecture for testing interconnects in SOC is proposed and demonstrated. In addition to stuck-at and open faults, this scheme can also detect delay faults and crosstalk glitches, which are otherwise very difficult to be tested under the traditional test schemes. IEEE Std. 1500 wrapper cells are modified to accommodate the test scheme. An efficient algorithm is proposed to construct ORs for SOC based on a graph model. Experimental results on MCNC benchmark circuits have been included to show the effectiveness of the algorithm. In all experiments, the scheme achieves 100% fault coverage with a small number of tests.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction.     

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.     

Analysis of Hamming count compaction scheme

Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique.Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.This work was funded in part by Sandia National Laboratory under contract SANDIA-27-6108.     

Test generation and scheduling for layout-based detection of bridgefaults in interconnects

This paper presents a new approach to detecting faults in interconnects; the novelty of the proposed approach is that test generation and scheduling are established using the physical characteristics of the layout of the interconnect under test. This includes critical area extraction and a realistic fault model for a structural methodology. Physical layout information is used to model the adjacencies in an interconnect and possible bridge faults with a weighted graph, which is then analyzed to appropriately compact the tests and schedule their execution for (early) detection of bridge faults. Generation and compaction of the test vectors are accomplished by calculating node and edge weight heuristics from the weighted adjacency graph. Simulation has been performed for unweighted and weighted fault models. Results on random interconnects and the local interconnect of a commercially available field-programmable gate array are provided. The advantage of the proposed approach is that, on average, early detection of faults is possible using significantly fewer tests than with previous approaches. A further advantage is that it represents a realistic alternative to adaptive testing because it avoids costly on-line test generation, while still having a small number of vectors