一种简化衬底模型的SOI MOS变容管模型

提出一种适用于反型层RF SOI MOS 变容管行为表征模型。在BSIMSOI的基础上,模型采用简化的衬底模型和外围射频寄生模型来表征变容管的射频寄生效应,同时采用T、π互转的方式提出参数提取算法。模型最终应用到华虹宏力SOI工艺提供的不同栅指,每栅指长度为1.6um、宽度为5 um的MOS变容管器件,并且在15GHz以下,模型与测量数据的CV、QV以及S参数有较好的拟合。在高频情况下,模型既保证了精度又解决了参数提取困难等问题。     

基于BSIM3模型的毫米波MOS变容管建模

提出了应用于毫米波段的MOS变容管的建模方法。针对标准0.18μm CMOS工艺,采用2D器件仿真软件MINIMOS,设计实现了积累型MOS变容管;并提出和分析了基于标准BSIM3模型的MOS变容管的等效电路模型;通过MINIMOS仿真,直接提取电路模型各寄生参数。该模型能方便地在电路设计软件中实现,并能预测最高达40 GHz频率范围内的变容管特性。     

一种新型的基于SOI MOSFET 衬底模型提取方法

衬底寄生网络建模和参数提取,对RF SOI MOSFET器件输出特性的模拟有着非常重要的影响。考虑BOX层引入的体区和Si衬底隔离,将源、体和衬底短接接地,测试栅、漏二端口S参数的传统测试结构,无法准确区分衬底网络影响。文章提出一种改进的测试结构,通过把SOI MOSFET的漏和源短接为信号输出端、栅为信号输入端,测试栅、漏/源短接二端口S参数的方法,把衬底寄生在二端口S参数中直接体现出来,并开发出一种解析提取衬底网络模型参数的方法,支持SOI MOSFET衬底网络模型的精确建立。采用该方法对一组不同栅指数目的SOI MOSFET进行建模,测量和模型仿真所得S参数在20GHz频段范围内得到很好吻合。     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

RF-CMOS建模:一种改进的累积型MOS变容管模型

提出一种改进的累积型MOS变容管射频模型,改进后模型方程可精确描述累积型MOS变容管全工作区域特性;模型方程连续,且任意阶次可导,至少三阶导数求解结果可实现与测试结果的精确拟合,解决了原模型可导但导数错误、变阻方程不连续等问题.模型最终应用到采用CSM(Chartered Semiconductor Manufacture Ltd)0.25μm RF-CMOS工艺制造的一30栅指(每指尺寸为长L=1μm,宽W=4.76μm)累积型MOS变容管建模中,测量和仿真所得C-V,R-V特性,品质因素以及高达39GHz S参数对比结果验证了模型的良好精度.     

太赫兹InP HEMT器件的建模

采用减小栅长(Lg)的方法可以显著提高磷化铟基高电子迁移率晶体管(InP HEMT)器件的直流和微波性能,并使器件的工作频率上升到太赫兹频段。采用T形栅工艺制备了70 nm栅长的InP HEMT器件,器件的直流跨导达到了2.87 S/mm,截止频率ft和最大振荡频率fmax分别为230 GHz和310 GHz。对器件的寄生参数进行了提取和去嵌入,得到了器件的本征S参数。采用经典的9参数模型拓扑结构对器件进行了小信号建模,模型仿真与测试结果拟合良好。针对电流的短沟道效应,采用电流分段的方法来拟合I-V曲线,取得了较好的拟合结果。最后采用Angelov模型对器件的电容进行建模,并最终建立了器件的大信号模型。     

基于TRL的3mm波段变容二极管对建模方法

本文在商用变容二极管的简化电路模型基础上,对非线性肖特基结和周围的无源结构进行了基于石英介质的TRL去嵌入建模分析,在考虑二极管无源区和封装环境各种寄生参量情况下,建立了精确的3mm波段二极管对电路模型.采用TRL算法,通过拟合初始二极管S参数曲线和TRL测试参数确定芯片电路模型中各集总参数元件数值.二极管对在片各项测试结果和基于改进的电路模型仿真结果相吻合.该二极管对电路模型建模方法可应用于毫米波亚毫米波混频倍频电路的准确分析与设计.     

AlGaN/GaN非凹槽混合阳极SBD射频性能及建模

基于大功率微波输能的需求,制备了新型AlGaN/GaN非凹槽混合阳极肖特基势垒二极管(SBD).对新型结构的器件进行了小信号建模,可用于微波输能电路设计.通过开路、短路去嵌结构法从小信号S参数中提取了器件的寄生电容、电感和电阻,结合去嵌后的S参数与直流I-V、C-V特性曲线提取了器件的本征参数.综合寄生和本征参数建立了器件的小信号模型,将模型仿真结果与器件的实测结果进行了对比,同时引入误差因子评估了模型的准确度.结果表明,在0.1～10GHz内,回波损耗相对误差小于4.1％,插入损耗相对误差小于3.7％,验证了所提出模型的可行性和准确性.     

多胞MOSFET器件的射频建模和参数提取（英文）

对纳米级金属氧化物半导体场效应管器件提出了改进的小信号模型.该改进模型中综合考虑了馈线的趋肤效应和器件多胞结构的影响.提取过程中,根据可缩放规律,由传统模型的参数推导出元胞参数.将模型应用于8×0.6×12μm(栅指数×栅宽×元胞数量)、栅长为90 nm的MOSFET器件在1~40 GHz范围内的建模,测试所得S参数和模型仿真所得S参数能够高度地吻合.     

多胞MOSFET器件的射频建模和参数提取

对纳米级金属氧化物半导体场效应管器件提出了改进的小信号模型.该改进模型中综合考虑了馈线的趋肤效应和器件多胞结构的影响.提取过程中, 根据可缩放规律, 由传统模型的参数推导出元胞参数.将模型应用于8×0.6×12 μm (栅指数×栅宽×元胞数量)、栅长为90 nm的MOSFET器件在1~40 GHz范围内的建模, 测试所得S参数和模型仿真所得S参数能够高度地吻合.     

3 nm环栅场效应管射频小信号等效电路模型

针对3 nm环栅场效应晶体管,提出了一种射频小信号等效电路模型及基于有理函数拟合的解析模型参数提取方法。首先,在关态条件下提取不受偏置影响的非本征栅/源/漏极电阻、栅到源/漏电容、衬底电容和电阻。然后,在不同偏置条件下提取受偏置影响的本征模型参数。使用Sentaurus TCAD和Matlab对器件进行仿真并拟合得到相关参数,在ADS中验证等效电路模型。结果表明,在10 MHz~300 GHz频率范围内,TCAD仿真与等效电路仿真S参数的最大误差低于2.69%,证实了所建立模型及建模方法的准确性。该项研究成果对射频集成电路设计具有参考价值。     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

一种新型的砷化镓平面肖特基变容管大信号模型

A millimeter wave large-signal model of GaAs planar Schottky varactor diodes based on a physical analysis is presented.The model consists of nonlinear resistances and capacitances of the junction region and external parasitic parameters.By analyzing the characteristics of the diode under reverse and forward bias,an extraction procedure of all of the parameters is addressed.To validate the newly proposed model,the PSVDs were fabricated based on a planar process and were measured using an automatic network...     

14 nm FinFET栅围寄生电容的建模与拟合

提出了一种基于保角映射方法的14 nm鳍式场效应晶体管(FinFET)器件栅围寄生电容建模的方法。对FinFET器件按三维几何结构划分寄生电容的种类,再借助坐标变换推导出等效电容计算模型,准确表征了不同鳍宽、鳍高、栅高和层间介质材料等因素对寄生电容的依赖关系。为了验证该寄生电容模型的准确性,对不同结构参数的寄生电容进行三维TCAD仿真。结果表明,模型计算结果与仿真结果的拟合度好,准确地反映了器件结构与寄生电容之间的依赖关系。     

A millimeter wave large-signal model of GaAs planar Schottky varactor diodes

A millimeter wave large-signal model of GaAs planar Schottky varactor diodes based on a physical analysis is presented.The model consists of nonlinear resistances and capacitances of the junction region and external parasitic parameters.By analyzing the characteristics of the diode under reverse and forward bias,an extraction procedure of all of the parameters is addressed.To validate the newly proposed model,the PSVDs were fabricated based on a planar process and were measured using an automatic network analyzer.Measurement shows that the model exactly represents the behavior of GaAs PSVDs under a wide bias condition from -10 to 0.6 V and for frequencies up to 40 GHz.     

尺寸可变的65nm多叉指射频CMOS器件模型提取与优化

通过对CMOS PSP直流核心模型进行STI参数的修正、探针电阻的引入和提取以及尺寸可变的源漏寄生电阻表达式的引入,呈现了一个尺寸可变的65 nm多叉指射频CMOS器件模型及其提取和优化方法.与实验数据比较结果表明,该模型及其提取和优化方法能够在14 GHz以内精确地预测器件性能.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz.