A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.     

流水线结构FFT/IFFT处理器的设计与实现

针对实时高速信号处理的要求，设计并实现了一种高效的FFT处理器。在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基—4算法，分级流水线以及定点运算结构。可以根据要求设置成4P点的FFT或IFFT。处理器可以对多个输入序列进行连续的FFT运算，消除了数据的输入输出对延时的影响。平均每完成一次N点FFT运算仅需要Ⅳ个时钟周期。整个设计基于Verilog HDL语言进行模块化设计。并在Altera公司的Cyclone Ⅱ器件上实现。     

Fast splitting alpha-rooting method of image enhancement: tensor representation.

In the tensor representation, a two-dimensional (2-D) image is represented uniquely by a set of one-dimensional (1-D) signals, so-called splitting-signals, that carry the spectral information of the image at frequency-points of specific sets that cover the whole domain of frequencies. The image enhancement is thus reduced to processing splitting-signals and such process requires a modification of only a few spectral components of the image, for each signal. For instance, the alpha-rooting method of image enhancement can be fulfilled through processing separately a maximum of 3N/2 splitting-signals of an image (N x N), where N is a power of two. In this paper, we propose a fast implementation of the a-rooting method by using one splitting-signal of the tensor representation with respect to the discrete Fourier transform (DFT). The implementation is described in the frequency and spatial domains. As a result, the proposed algorithms for image enhancement use two 1-D N-point DFTs instead of two 2-D N x N-point DFTs in the traditional method of alpha-rooting.     

Efficient VLSI architectures for fast computation of the discreteFourier transform and its inverse

In this paper, we propose two new VLSI architectures for computing the N-point discrete Fourier transform (DFT) and its inverse (IDFT) based on a radix-2 fast algorithm, where N is a power of two. The first part of this work presents a linear systolic array that requires log₂ N complex multipliers and is able to provide a throughput of one transform sample per clock cycle. Compared with other related systolic designs based on direct computation or a radix-2 fast algorithm, the proposed one has the same throughput performance but involves less hardware complexity. This design is suitable for high-speed real-time applications, but it would not be easily realized in a single chip when N gets large. To balance the chip area and the processing speed, we further present a new reduced-complexity design for the DFT/IDFT computation. The alternative design is a memory-based architecture that consists of one complex multiplier, two complex adders, and some special memory units. The new design has the capability of computing one transform sample every log₂ N+1 clock cycles on average. In comparison with the first design, the second design reaches a lower throughput with less hardware complexity. As N=512, the chip area required for the memory-based design is about 5742×5222 μm², and the corresponding throughput can attain a rate as high as 4M transform samples per second under 0.6 μm CMOS technology. Such area-time performance makes this design very competitive for use in long-length DFT applications, such as asymmetric digital subscriber lines (ADSL) and orthogonal frequency-division multiplexing (OFDM) systems     

A new IDCT-DFT relationship reducing the IDCT computational cost

This paper reconsiders the discrete cosine transform (DCT) algorithm of Narashima and Peterson (1978) in order to reduce the computational cost of the evaluation of N-point inverse discrete cosine transform (IDCT) through an N-point FFT. A new relationship between the IDCT and the discrete Fourier transform (DFT) is established. It allows the evaluation of two simultaneous N-point IDCTs by computing a single FFT of the same dimension. This IDCT implementation technique reduces by half the number of operations     

Fast computation of the two-dimensional generalised Hartleytransforms

The two-dimensional generalised Hartley transforms (2-D GDHTs) are various half-sample generalised DHTs, and are used for computing the 2-D DHT and 2-D convolutions. Fast computation of 2-D GDHTs is achieved by solving (n₁+(n₀₁/2))k₁+(n₂+(n₀₂ /2))k₂=(n+(½))k mod N, n₀₁, n₀₂ =1 or 0. The kernel indexes on the left-hand side and on the right-hand side belong to the 2-D GDHTs and the 1-D H₃, respectively. This equation categorises N×N-point input into N groups which are the inputs of a 1-D N-point H₃. By decomposing to 2-D GDHTs, an N×N-point DHT requires a 3N/2ⁱ 1-D N/2ⁱ-point H₃, i=1, ..., log₂N-2. Thus, it has not only the same number of multiplications as that of the discrete Radon transform (DRT) and linear congruence, but also has fewer additions than the DRT. The distinct H ₃ transforms are independent, and hence parallel computation is feasible. The mapping is very regular, and can be extended to an n-dimensional GDHT or GDFT easily     

An On-Sensor Bit-Serial Column-Parallel Processing Architecture for High-Speed Discrete Fourier Transform

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256$,times,$256-point DFT for 8-b image data, the processing time is estimated to be 2 ms at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing.     

A 64-point Fourier transform chip for video motion compensationusing phase correlation

Details of a new low power fast Fourier transform (FFT) processor for use in digital television applications are presented. This has been fabricated using a 0.6-μm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-time video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm² and dissipates 1 W. The chip design is based on a novel VLSI architecture which has been derived from a first principles factorization of the discrete Fourier transform (DFT) matrix and tailored to a direct silicon implementation     

基于改进FFT算法的OFDM调制/解调模块设计

文章对传统FFT算法进行了改进,改进后的算法将N点DFT分解成二维√N点DFT的组合,在结构上更适合于用流水线方式实现FFT.文章首先对算法进行了推导,然后基于该算法设计了一个64点、32位字长的定点IFFT/FFT模块,用于802.11a中OFDM的调制/解调.与传统的流水线FFT比较,该模块中的复数乘法运算全部采用移位相加操作完成,因而消除了乘法器及旋转因子ROM的使用,降低了功耗.最后,对该模块进行了验证仿真.结果表明,在流水线饱和的情况下,该模块完成一个64点的FFT运算只需要8个时钟周期,在20MHZ时钟频率下,该模块的功耗为0.26W,完全能满足移动通信中对于高速度、低功耗的要求.     

二维级联流水结构大点数FFT运算器实现研究

大点数快速傅里叶变换(FFT)运算在雷达、通信信号侦察中有广泛应用,其基于现场可编程门阵列(FPGA)的实现方法有重要的研究价值。推导出点数为N的大点数FFT运算分解为2级小点数FFT运算级联的运算公式,在此基础上给出其实现步骤,从流水线结构设计、基本运算单元以及地址生成等方面详细介绍一维列(行)变换的工程实现方法,并给出列、行变换之间所乘旋转因子的压缩算法。工程实际应用表明,该大点数FFT运算器具有变换速度快、调试方便及可在单片FPGA实现的优点。     

A CORDIC processor for FFT computation and its implementation usinggallium arsenide technology

In this paper, the architecture and the implementation of a complex fast Fourier transform (CFFT) processor using 0.6 μm gallium arsenide (GaAs) technology are presented. This processor computes a 1024-point FFT of 16 bit complex data in less than 8 μs, working at a frequency beyond 700 MHz, with a power consumption of 12.5 W. The architecture of the processor is based on the COordinate Rotation DIgital Computer (CORDIC) algorithm, which avoids the use of conventional multiplication-and-accumulation (MAC) units, but evaluates the trigonometric functions using only add and shift operations, Improvements to the basic CORDIC architecture are introduced in order to reduce the area and power of the processor. This together with the use of pipelining and carry save adders produces a very regular and fast processor, The CORDIC units were fabricated and tested in order to anticipate the final performance of the processor. This work also demonstrates the maturity of GaAs technology for implementing ultrahigh-performance signal processors     

A reconfigurable 8 GOP ASIC architecture for high-speed datacommunications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated, and synthesized. The proposed architecture compares favorably to classical DSP and FPGA solutions. It differs from general-purpose reconfigurable computing (RC) platforms by emphasizing high-speed application-specific computations over general-purpose flexibility. The proposed architecture can he used to realize any one of several functional blocks needed for the physical layer implementation of data communication systems operating at symbol rates in excess of 125 Msymbols/s. Multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions): real and complex FIR/IIR filtering, least mean square (LMS)-based adaptive filtering, discrete Fourier transforms (DFT), and direct digital frequency synthesis (DDFS) at up to 125 Msamples/s. All of the modes are mapped onto a common, regular data path with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks     

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi‐standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual‐clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi‐operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance‐area trade‐off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.     

SOC芯片DFT研究与设计

文章首先介绍了SOC系统的DFT设计背景和DFT的各种测试机理,包括基于功能的总线测试机理、基于边界扫描链的测试机理、基于插入扫描电路的测试机理以及基于存储器自测试的测试机理。然后以某专用SOC芯片为例提出了SOC电路的DFT系统构架设计和具体实现方法。主要包括：含有边界扫描BSD嵌入式处理器的边界扫描BSD设计,超过8条内嵌扫描链路的内部扫描SCAN设计,超过4个存储器硬IP的存储器自测试MBIST,以及基于嵌入式处理器总线的功能测试方法。最后提出了该SOC系统DFT设计的不足。     

A scaled DCT architecture with the CORDIC algorithm

This paper presents an efficient approach for computing the N-point (N=2ⁿ) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture     

Discrete cosine transform processor using a c.c.d. programmable transversal filter

The design and performance of a compact discrete-cosine prime-transform processor using a charge-coupled-device programmable transversal filter is reported. The c.c.d. design used here allows the required operations of data permutation and correlation to be performed in the same device. In addition, this arrangement permits an N-stage c.c.d. filter to be used for implementation of an N-point transform. This represents a factor-of-two reduction in c.c.d. stages over previously reported systems.     

Spectrum shaping in N-channel QPSK-OFDM systems

A compact time-domain treatment of a complete spectrum shaped N-channel orthogonal FDM system is presented, enabling practical DSP algorithms for modulation and demodulation to be clearly identified. The resulting DSP architecture is an alternative to previously described OQPSK-OFDM systems and directly provides the two complex samples per symbol required for symbol timing recovery. The paper also discusses parameter selection for the polyphase shaping filters and compares simulation results of power spectral density for shaped and unshaped systems. Simulation shows that shaped systems can closely approach the ideal transmission spectrum even for modest values of N     

改进的DFT正弦信号频率估计

通过分析Candan算法和2N点DFT算法的性能,本文提出了一种改进的基于DFT的正弦信号频率估计算法。在对原始信号进行必要的离散化预处理后,在粗估计阶段利用Candan算法估计出频率偏差后,利用该频偏对原始信号进行频率修正。然后对修正后的原始信号进行2N点DFT算法精估计。由于增加了原始信号的频率修正步骤,该算法发挥了Candan算法和2N点DFT算法的优点,同时避免了其缺点。仿真结果表明,在相对频偏为任意值时,改进算法频率估计的均方根误差均接近克拉美罗下限,并且估计性能优于现有的频率估计算法。      

基于星座符号序列局部相位旋转的低峰均功率比滤波器组多载波结构优化

针对基于离散傅里叶变换(DFT)扩频的低峰均功率比滤波器组多载波(LP-FBMC)结构需要额外传输边带信息(SI)等问题,该文提出一种基于星座符号序列局部相位旋转的无SI优化结构.考虑到SI是由LP-FBMC在发送端对4种信号传输形式进行选择而产生,结合这4种形式解调后的星座符号序列与原符号序列的关系,采用对星座符号序...     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements