A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET''''S

The hot-carrier-induced oxide regions in the front and back interfaces are systemati-cally studied for partially depleted SOI MOSFET's. The gate oxide properties are investigated forchannel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stressexperiments with three typical hot-carrier injection, i.e., the maximum gate current, maximumsubstrate current and parasitic bipolar transistor action. Experiments show that PMOSFET's     

A thorough investigation of hot-carrier-induced gate oxide breakdown in partially depleted N- and P-channel SIMOX MOSFETs

In this paper, the hot-carrier-injected oxide region in the front interfaces is systematically investigated for partially depleted silicon-on-insulator (PDSOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) devices fabricated on a SIMOX wafer. The gate oxide properties associated with channel hot-carrier effects are investigated and the hot-carrier-induced device degradations are analyzed using stress experiments with three main types of hot-carrier injections-maximum gate current, maximum substrate current and parasitic bipolar transistor action. Based on experimental results, the influence of these injected carriers on the gate oxide properties is clarified. As a matter of fact, NMOSFETs degradation mechanism is shown to be caused by hot holes injected into the drain side of the gate oxide, and electrons trapped in the gate oxide can accelerate the gate oxide breakdown. PMOSFETs degradation mechanism depends on the biasing conditions. For the first time, we conclude that the electrical characteristics of NMOSFETs are significantly different from that of PMOSFETs after the gate oxide breakdown. An extensive discussion of the experimental results is provided.     

A STUDY ON HOT-CARRIER-INDUCED GATE OXIDE BREAKDOWN IN PARTIALLY DEPLETED SIMOX MOSFET’S

The hot-carrier-induced oxide regions in the front and back interfaces are systematic-cally studied for partially depleted SOI MOSFET‘s .The gate oxide properties are investigated for channel hot-carrier effects.The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection,i.e.the maximum gate current, maximum substrate current and parasitic bipolaf transistor action.Experiments show that PMOSFET‘s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET‘s degradation is caused by hot holes.This paper reports for the first time that the electric characteristics of NMOSFET‘s and PMOSFET‘s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided.     

沟道热载流子导致的 PDSOI NMOSFET's击穿特性

对热载流子导致的 SIMOX衬底上的部分耗尽 SOI NMOSFET's的栅氧化层击穿进行了系统研究 .对三种典型的热载流子应力条件造成的器件退化进行实验 .根据实验结果 ,研究了沟道热载流子对于 SOI NMOSFET's前沟特性的影响 .提出了预见器件寿命的幂函数关系 ,该关系式可以进行外推 .实验结果表明 ,NMOSFET's的退化是由热空穴从漏端注入氧化层 ,且在靠近漏端被俘获造成的 ,尽管电子的俘获可以加速 NMOSFET's的击穿 .一个 Si原子附近的两个 Si— O键同时断裂 ,导致栅氧化层的破坏性击穿 .提出了沟道热载流子导致氧化层击穿的新物理机制     

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET

A simple analytical model for deriving the front and the back gate threshold voltages of a short-channel fully-depleted SOI MOSFET is presented. Taking into account the lateral variations of the front and the back surface potentials, we obtain two-dimensional potential distributions in the fully depleted silicon body, the front oxide layer, and the back oxide layer. From the obtained two- dimensional potential in the silicon body, the minimum values of both front and back surface potentials are derived and used to describe both front and back gate threshold voltages as closed-form expressions in terms of various device geometry parameters and applied bias voltages. Obtained results are found to be in good agreement with the numerically simulated results.     

Comparative analysis of hot electron injection and induced devicedegradation in scaled 0.1 μm SOI n-MOSFETs using Monte Carlosimulation

A self-consistent Monte Carlo (MC) simulator is employed to investigate and compare hot electron phenomena in three competing design strategies for 0.1 μm SOI n-MOSFETs operating under low voltage conditions, i.e., V_d considerably less than the Si-SiO₂ injection barrier height φ_b. Simulations of these designs reveal that non-local carrier transport effects and two-dimensional current how play a significant role in determining the relative rate and location of hot electron injection into both the front and back oxides. Specifically, simulations indicate that electron-electron interactions near the drain edge are a main source of electron energies exceeding φ_b. The hot electron injection distributions are then coupled with an empirical model to generate interface state distributions at both the front and back oxide interfaces. These interface states are incorporated into a drift-diffusion simulator to examine relative hot-electron-induced device degradation for the three 0.1 μm SOI designs. Simulations suggest that both the Si layer thickness and doping distribution affect device sensitivity to hot-electron-induced interface states. In particular, the simulations show that a decrease in the channel doping results in increased sensitivity to back oxide charge. In the comparison of the heavily-doped designs, the design with a thinner T_Si experiences significantly more hot-electron-induced oxide damage in the back oxide and more degradation from the charged states at the back interface     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs

In this work, single transistor latch effects induced by total dose irradiation for 0.13 μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones.     

Dose rate dependence of the back gate degradation in thin gate oxide PD-SOI MOSFETs by 2-MeV electron irradiation

The degradation of the electrical properties of thin gate oxide PD-SOI n-MOSFETs by 2-MeV electrons at different dose rates is presented. The degradation of the back channel and its dependence on dose rate are clarified. The characteristics of the PD-SOI MOSFETs are degraded, and the degradation becomes higher for a low dose rate. The magnitude of the hysteresis characteristics in the drain current becomes smaller after irradiation, and the degradation for a low dose rate is higher than for a high dose rate. It is found that the degradation of the front characteristics is related to the back gate degradation by the coupling effect.     

Simulation of partially and near fully depleted SOI MOSFET devices and circuits using SPICE compatible physical subcircuit model

A four-terminal physical subcircuit model for floating body (FB) partially depleted (PD) and near fully depleted (near FD) SOI CMOS devices is presented. The model accounts for the unique characteristics of PD devices associated with the drain (V_ds) induced floating body effects. Unlike other models, the proposed circuit model accounts physically for the back MOSFET device, and accurately predicts the bias dependence of the current kink in near FD devices. It allows for proper capacitance scaling and more accurate simulations related to the front and back oxides/channels. Self-heating effects related to the low thermal conductivity of the back oxide are also included. The circuit model is SPICE compatible and provides insights for understanding optimal device design needs for high performance. A simple technique for extracting the model parameters is described. The model is verified by the good agreement of the simulation results with the experimental data. The predictive capabilities of the subcircuit model are supported by circuit level simulation examples.     

Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s

New 3-D analytical models of front and back gate threshold voltages for fully depleted SOI MOSFET’s have been described here. The present models take into account the contributions of all the three paths of conduction such as front gate oxide-silicon, back gate oxide-silicon and side wall oxide-silicon interfaces in mesa isolated structure of such MOSFET’s. In order to do this, 3-D Poisson’s equation has been solved analytically with suitable boundary conditions to obtain an explicit expression of electrostatic potential within fully depleted SOI film with uniform doping concentration. With the help of this expression, the compact and closed form formulae of front and back gate threshold voltages under various conditions have been established. In addition to this, the closed form expressions of biasing counterparts of front and back threshold voltages i.e. respective back and front gate biases have also been reported in order to decide required operational modes of both interfaces of the device. The calculated results of the threshold voltages have been validated with available numerical data.     

New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at V/sub G/>V/sub D/. We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.     

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.     

超深亚微米部分耗尽SOI NMOSFET关态应力下前栅和背栅晶体管损伤研究

The hot-carrier effect charactenstic in a deep submicron partially depleted SOI NMOSFET is investigated. Obvious hot-carrier degradation is observed under off-state stress.The hot-carrier damage is supposed to be induced by the parasitic bipolar effects of a float SOI device.The back channel also suffers degradation from the hot carrier in the drain depletion region as well as the front channel.At low gate voltage,there is a hump in the sub-threshold curve of the back gate transistor,and it does not shift in the same way as the main transistor under stress.While under the same condition,there is a more severe hot-carrier effect with a shorter channel transistor. The reasons for those phenomena are discussed in detail.     

Reduction of leakage current at the gate edge of SDB SOI NMOStransistor

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, ~2500 Å) and fully depleted (FD, ~800 Å) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES IIb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to ~pA and no hump was seen on the drain current curve     

New hot-carrier degradation mode and lifetime prediction method inquarter-micrometer PMOSFET

Hot-carrier-induced device degradation has been studied for quarter-micrometer level buried-channel PMOSFETs. It was found that the major hot-carrier degradation mode for these small devices is quite different from that previously reported, which was caused by trapped electrons injected into the gate oxide. The new degradation mode is caused by the effect of interface traps generated by hot hole injection into the oxide near the drain in the saturation region. DC device lifetime for the new mode can be evaluated using substrate current rather than gate current as a predictor. Interface-trap generation due to hot-hole injection will become the dominant degradation mode in future PMOSFETs     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Analysis of temperature-induced saturation threshold voltage degradation in deep-submicrometer ultrathin SOI MOSFETs

This paper presents a systematic study of the temperature lowering influence on the saturation threshold voltage degradation in ultrathin deep-submicrometer fully depleted silicon-on-insulator (SOI) MOSFETs. It is observed that the difference between the threshold voltage obtained with low and high drain bias, increases at lower temperatures for nMOSFETs, whereas it is weakly temperature-dependent for pMOSFETs. Experimental results and two-dimensional numerical simulations are used to support the analysis. The influence of applied back gate bias on threshold voltage variation is also studied. It is demonstrated that the higher doping level into the body region provided by the halo ion implantation associated to the floating-body increases both the multiplication factor and the parasitic bipolar gain as the temperature is lowered contributing to the threshold voltage degradation. The absence of halo implantation efficiently improves this degradation. The use of double gate structure, even with high body doping level, suppress the saturation threshold voltage degradation in cryogenic operation.     

Simulation and two-dimensional analytical modeling of subthresholdslope in ultrathin-film SOI MOSFETs down to 0.1 μm gate length

The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 μm. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S -factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found