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NoC:下一代集成电路主流设计技术 总被引:16,自引:0,他引:16
从SoC的定义出发,依据“PC参考系准则”、“十年变革规律”、“半导体技术发展规律”等基本规律,提出并论证了“NoC是下一代集成电路主流设计技术”的观点,概括了NoC基础理论体系的主要研究领域;简要分析了集成电路NoC体系结构领域可能的关键技术。NoC技术从体系结构上彻底解决了SoC的总线结构所固有的三大问题:由于地址空间有限而引起的扩展性问题,由于分时通讯而引起的通讯效率问题,以及由于全局同步而引起的功耗和面积问题。 相似文献
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With the feature size of semiconductor technology reducing and intellectual property (IP) cores increasing, on-chip interconnection network architectures have a great influence on the performance and area of system-on-chip (SoC) design. Focusing on trade-off performance, cost and implementation, a regular network-on-chip (NoC) architecture which is mesh-connected rings (MCR) interconnection network is proposed. The topology of MCR is simple, planar and scalable in architecture, which combines mesh with ring. A detailed theoretical analysis for MCR and mesh is given, and a simulation analysis based on the virtual channel router with wormhole switching is also presented. The results compared with the general mesh architecture show that MCR has better performance, especially in local traffics and low loads, and lower cost. 相似文献
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Network on Chip (NoC) has been proposed as a solution for addressing the challenges in System on Chip (SoC) design. Designing a topology and its routing schemes are vital problems in a NoC. One of the major challenges that designers face today in 3D integration is how to route the data packets within a layer and across the layers in a scalable and efficient manner. In any 3D topology, minimizing the amount of data packet transmissions during the routing is still an open problem. Any efficient traditional routing schemes should avoid deadlocks and minimize network congestion from a source node to a destination node. 相似文献
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The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even. 相似文献
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针对专用片上网络(Network on Chip,NoC)全局通信事务管理和可靠性设计问题,提出片上网络监控器的概念,用于获取全局网络实时状态信息及执行路径分配算法,基于此提出一种动态路由机制DyRS-NM.该机制能检测和定位NoC中的拥塞和故障链路,并能区分瞬时和永久性链路故障,采用重传方式避免瞬时故障,通过重新路由计算绕开拥塞和永久性故障.设计实现了RTL级网络监控器和与之通信的容错路由器模块,并将MPEG4解码器应用映射至基于网络监控器的4×4Mesh结构NoC体系结构中,验证了系统性能以及面积功耗开销.相比静态XY路由和容错动态路由FADR,DyRS-NM机制在可接受的开销代价下获得了更优的性能. 相似文献
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基于通讯的NoC设计 总被引:2,自引:0,他引:2
近年来,一种全新的集成电路体系结构——Network on Chip(NoC)已经成为徽电子学科研究的热点佃题之一,其核心思想是将计算机网络技术移植到芯片设计中来,从体系结构上彻底解决片上通讯的瓶颈问题。文章提出了一种基于通讯的NoC设计方法,通过监控和协调NoC的网络通讯来获得更好的性能.并总结了实现该设计方法所必须研究的关键技术。 相似文献
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On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems 总被引:2,自引:0,他引:2
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(9):1173-1186
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Leary G. Srinivasan K. Mehta K. Chatha K.S. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(5):674-687
The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches. 相似文献
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Networks-on-chip (NoC), a new system on chip (SoC) paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh (2DDgl-Mesh) for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 (a network simulator) and CINSIM (a component based interconnection simulator) under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our architecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models. 相似文献
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Networks-on-chip (NoC), a new system on chip (SoC) paradigm, has become a great focus of research by many groups during the last few years. Among all the NoC architectures that have been proposed until now, 2D-Mesh has proved to be the best architecture for implementation due to its regular and simple interconnection structure. In this paper, we propose a new interconnect architecture called 2D-diagonal mesh (2DDgl-Mesh) for on-chip communication. The 2DDglMesh is almost similar to traditional 2D-Mesh in aspects of cost, area, and implementation, but it can outperform the later in delay. The both architectures are compared by using NS-2 (a network simulator) and CINS1M (a component based interconnection simulator) under the same traffic models and parametric conditions. The results of comparison show that under the proposed architecture, the packets can almost always be routed to their destinations in less time. In addition, our archi- tecture can sometimes perform better than 2D-Mesh in drop ratio for special fixed traffic models. 相似文献
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任意拓扑结构战术地域分组交换网的性能分析 总被引:1,自引:0,他引:1
本文以战术地域分组交换网为基础建立具有不规则拓扑结构网络模型,在给出网络的拓扑结构、网络用户业务量和路由选择算法的条件下,提出了一种计算网络链路传输业务量的方法,并用于分析网络的传输性能。同时,还用计算机仿真方法对同一网络进行模拟。分析结果说明:这类通信网的路由选择算法的设计应更重视网络内部流量的均匀分配 相似文献
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Khalid Latif Amir-Mohammad Rahmani Ethiopia Nigussie Tiberiu Seceleanu Martin Radetzki Hannu Tenhunen 《Journal of Electronic Testing》2013,29(3):431-452
We present a novel Partial Virtual channel Sharing (PVS) NoC architecture which reduces the impact of faults on performance and also tolerates faults within the routing logic. Without PVS, failure of a component impairs the fault-free connected components, which leads to considerable performance degradation. Improving resource utilization is key in enhancing or sustaining performance with minimal overhead when faults or overload occurs. In the proposed architecture, autonomic virtual-channel buffer sharing is implemented with a novel algorithm that determines the sharing of buffers among a set of ports. The runtime allocation of the buffers depends on incoming load and fault occurrence. In addition, we propose an efficient technique for maintaining the accessibility of a processing element (PE) to the network even if its router is faulty. Our techniques can be used in any NoC topology and for both, 2D and 3D NoCs. The synthesis results for an integrated video conference application demonstrate 22 % reduction in average packet latency compared to state-of-the-art virtual channel (VC) based NoC architecture. Extensive quantitative simulation has been carried out with synthetic benchmarks. Simulation results reveal that the PVS architecture improves the performance significantly in presence of faults, compared to other VC-based NoC architectures. 相似文献
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Ogras U.Y. Marculescu R. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(7):693-706
Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology. 相似文献