Hydrogen etching for semiconductor materials in plasma doping experiments

The etching effects of hydrogen plasma for semiconductor materials including single crystalline silicon, polycrystalline silicon, silicon dioxide, and aluminum in plasma immersion ion implantation (PHI) doping experiments have been investigated. Etching can alter device structure and affect implant profile and dose. The effects of varying different PIII process parameters such as pulse potential, pulse repetition frequency, and substrate temperature are presented. The experimental data show that the spontaneous etching by hydrogen radicals enhanced by ion bombardment is responsible for the etching phenomena that occurs at the material surface. A model is used to calculate the retained implant dose and impurity profile when the etching effect is considered.     

Solar‐grade boron emitters by BF3 plasma doping and role of the co‐implanted fluorine

We investigate the electrical properties and dopant profiles of boron emitters performed by plasma immersion ion implantation from boron trifluoride (BF₃) gas precursor, thermally annealed and passivated by silicon oxide/silicon nitride stacks. High thermal budgets are required for doses compatible with screen‐printed metal pastes, to reach very good activation rates. However, if good sheet resistances and saturation current densities may be obtained, we met strong limitations of the implied open‐circuit voltage of the n‐type Czochralski silicon substrates, which is incompatible with high‐efficiency solar cells. Such limitations are not encountered with beamline where pure B⁺ ions are implanted. Efforts on the passivation quality may improve the implied open‐circuit voltage but are not sufficient. We provide experimental comparison between beamline and plasma immersion allowing us to discriminate the causes explaining this observation (implantation technique or ion specie used) and to infer our interpretation: The co‐implantation of fluorine seems to indirectly impact the lifetime of the core substrate after thermal annealing. Copyright © 2015 John Wiley & Sons, Ltd.     

Layer-transfer process for silicon-on-insulator with improved manufacturability

We observe hydrogen platelet buildup in single-crystalline silicon caused by hydrogen-plasma processing. The platelets are aligned along a layer of lattice defects formed in silicon before the plasma processing. The buried-defect layer is formed by either silicon-into-silicon or argon-into-silicon implantation. We discuss the platelet nucleation, growth, and merge phenomena and discuss applicability of the plasma hydrogenation to silicon-on-insulator (SOI) wafer fabrication by layer transfer.     

Formation of Ge nanocrystals in a silicon dioxide layer using pulsed plasma-immersion ion implantation

Pulsed plasma-immersion ion implantation (PIII) or Pulsed PLAsma Doping (P²LAD) is known as a cost effective solution for ultra shallow junction formation due to its capability to implant doping species at ultra-low energies (0.05–5 keV), the advantages of P²LAD, high concentration and sharp distribution of the implanted species, also make this technique a good candidate to fabricate nanocrystals (NCs) within silicon dioxide (SiO₂) layer. In this work, we report Ge NC fabrication within a SiO₂ layer by using the pulsed PIII technique for the first time. GeH₄ (4 sccm) and He (100 sccm) gases were flown to the plasma chamber, and a voltage of 4.5 kV was applied. After pulsed PIII process, furnace annealing was performed at 900 °C in nitrogen atmosphere for Ge agglomeration. By using such a process, we fabricated non-volatile memory devices and obtained relevant program/erase, retention, and cycling characteristics.     

利用PⅢ技术改变框架与EMC间附着力的研究

利用等离子体浸没式注入(PⅢ)技术,使用O2,N2,CO和CO2做气体源,对镀镍铜框架表面进行处理。拉力测试实验结果表明,与未经处理的空白框架相比,经过CO和CO2等离子体注入处理的镀镍铜框架与环氧塑封料(EMC)间的附着力分别提高了约35倍和12倍,而在使用O2和N2等离子体注入处理的情况下,附着力基本没有变化。通过扫描电子显微镜(SEM)对处理前后的框架表面观察,发现PⅢ处理并未引起表面粗糙度的显著变化。利用X射线电子能谱(XPS)分析,可以发现在经过CO或CO2等离子体注入处理后的框架表面有羰基出现。基于这些结果,分析了导致附着力提升的机理。     

应用ICP-AES表征高剂量氧注入过程中的金属污染

研究了采用感应耦合等离子体原子发射光谱技术表征高剂量氧注入单晶硅制备SIMOX SOI材料过程中金属杂质污染的有效性.同时研究了采用强酸清洗、加SiO2 膜覆盖等方法对降低污染程度的效果.利用ICP技术可以对大面积或整个硅片进行采样,检测结果是一种整体的平均效果.采用强流氧注入机进行高剂量氧注入,发现金属杂质污染元素主要是Al、Ar、Fe、Ni;注入后强酸清洗样品可有效降低Al污染;6 0nm厚的二氧化硅注入保护膜可阻挡一半的上述金属污染.     

SOI／SIMOX材料导电类型反型的研究

采用大剂量氧离子注入（１７０ｋｅＶ，１．８×１０１８＋／ｃｍ２）ｐ型单晶硅，高温退火（１３００℃，６ｈ）后形成ＳＯＩ－ＳＩＭＯＸ（ＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ－ＳｅｐａｒａｔｉｏｎｂｙＩｍｐｌａｎｔａｔｌｏｎｏｆＯｘｙｇｅｎ）样品。俄歇电子能谱仪和扩展电阻仪测试表明，该样品表层硅膜的导电类型由ｐ型反型为ｎ型。ＳＩＭＯＸ样品的反型是硅中的氧施主所致，由近自由电子的类氦模型计算，ＳＩＭＯＸ样品中氧施主的电离能为０．１５ｅＶ，与早期文献报导的实验值一致。     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

全方位离子注入技术

等离子体离子注入(PII)是一种用于材料表面改性的新型离子注入技术。PII分为两类,用于金属表面改性时称为等离子体源离子注入技术(PSII),用于半导体材料表面改性时称为等离子体浸没离子注入(PIII)。本文介绍一种新的PII技术,称为全方位离子注入(All Orientation Ion Implantation),采用横磁瓶电子迴旋共振等离子体源,样品上的负高压可以是直流、交流或脉冲方式,本装置可以工作在离子注入和动态离子束混合两种模式。     

注氮剂量对SOI材料埋氧中电荷密度的影响

为对SIMOX SOI材料进行抗总剂量辐照加固,可向材料的埋氧（BOX）层中注入一定剂量的氮元素。但是,研究发现,注氮埋层中的初始电荷密度皆为正值且密度较高,而且随着注氮剂量的增加而上升。注氮埋层中较高的正电荷密度可归因于氮在退火过程中在Si-BOX界面的积累。另外,与注氮埋层不同的是,注氟的埋层却显示出具有负的电荷密度。为得到埋层的电荷密度,测试用样品制成金属-埋氧-半导体(MBS)电容结构,用于进行高频C-V测量分析。     

Measurement and modeling of circuit speed of CMOS on oxygen-implanted SOI

The dependence of the stage delay of CMOS ring oscillators on the voltage applied to the underlying silicon substrate has been investigated for SOI substrates formed by high-dose oxygen ion implantation. Improvements in speed of up to 30 percent are produced when the silicon under the isolating oxide is depleted. This situation occurs naturally for zero applied voltage when the substrate is lightly doped p-type and gives the oxygen-implanted SOI similar speed performance to other forms of SOI with thicker isolation layers. The increased speed is in good agreement with predictions made using SPICE simulation and modeled circuit capacitances.     

The effect of post-oxygen-implant annealing temperature on the channel mobilities of CMOS devices in oxygen-implanted silicon-on-insulator structures

The effects of post-oxygen-implant annealing temperature on the characteristics of MOSFET's in oxygen-implanted silicon-on-insulator (SOI) substrates are studied. The results show significant improvements in the electron and hole mobilities near the silicon/buried-oxide interface and in the electron mobility of the front-gate n-channel transistors in SOI substrates with higher post-oxygen-implant annealing temperature. The improvements in the transistor characteristics hence are attributed to the annihilation of oxygen precipitates and the reduction of defect density in the residual silicon film. By comparing the ring oscillators fabricated in SOI substrates annealed at 1150°C and 1250°C after oxygen implantation, a speed improvement of 15 percent is observed in substrates annealed at higher temperature.     

Hardening silicon-on-insulator nMOSFETs by multiple-step Si+ implantation

A novel technique is proposed to improve total irradiation dose (TID) hardness of buried oxides in a 0.13 μm silicon-on-insulator (SOI) technology. Multiple-step Si ion implantation is implemented to avoid silicon film amorphization. Each implant step introduces silicon ion implantation of a lower dose into buried oxides which creates an amorphous/crystalline (a/c) interface inside the silicon layer. Rapid thermal annealing (RTA) removes implant-induced lattice damages by silicon recrystallization reflected in a/c interface moving towards the top silicon surface. The thermal process prevents top silicon layers from total amorphization arising in the technique of single high dose implantation method. X-ray Diffraction (XRD) spectrum confirms the existence of the a/c interface and determines the single implant dose. Experimental results on pseudo-MOS and H-gate partially-depleted SOI n-type MOSFETs show radiation tolerance up to 1.0 Mrad(Si) though introduced metastable electron traps lead to I–V hysteresis and bias instabilities.     

Effects of nitrogen incorporation by plasma immersion ion implantation on electrical characteristics of high-k gated MOS devices

Nitridation treatments are generally used to enhance the thermal stability and reliability of high-k dielectric. It is observed in this work that, the electrical characteristics of high-k gated MOS devices can be significantly improved by a nitridation treatment using plasma immersion ion implantation (PIII). Equivalent oxide thickness, (EOT) and interface trap density of MOS devices are reduced by a proper PIII treatment. At an identical EOT, the leakage current of devices with PIII nitridation can be reduced by about three orders of magnitude. The optimal process conditions for PIII treatment include nitrogen incorporation through metal gate, ion energy of 2.5 keV, and implantation time of 15 min.     

Thermal stability of tantalum nitride diffusion barriers for Cu metallization formed using plasma immersion ion implantation

Plasma immersion ion implantation (PIII) technique was employed to form Tantalum nitride diffusion barrier films for copper metallization on silicon. Tantalum coated silicon wafers were implanted with nitrogen at two different doses. A copper layer was deposited on the samples to produce Cu/Ta(N)/Si structure. Samples were heated at various temperatures in nitrogen ambient. Effect of nitrogen dose on the properties of the barrier metal was investigated by sheet resistance, X-ray diffraction and scanning electron microscopy measurements. High dose nitrogen implanted tantalum layer was found to inhibit the diffusion of copper up to 700 °C.     

磷离子注入对部分耗尽SOI MOS总剂量背栅效应的影响

本文研究了背栅磷离子注入加固技术对部分耗尽绝缘体上硅（silicon-on-insulator, SOI）MOS器件抗总剂量辐射性能提升的机理。认为可以对背栅沟道处进行磷离子注入,改变界面处的离子浓度分布,通过引入电子陷阱,抵消背栅界面陷阱俘获正电荷,从而改善背栅效应,提高器件的抗辐射性能。通过用高浓度磷离子对部分耗尽SOI NMOS器件背栅进行离子注入,大大减小了器件的背栅效应,实验器件的抗辐射能力能够达到1M rad（Si）。     

利用射频与高压直接耦合等离子体注入进行不锈钢表面改性

介绍了一种新的等离子体离子注入在不锈钢表面改性上的应用.将高压脉冲和射频脉冲直接耦合到工件上,不需外部等离子体源,利用工件自身加射频产生等离子体,随后施加高压对不锈钢表面进行了注氮处理.XPS分析显示,在基体表面有氮元素存在,说明实现了射频与高压直接耦合的离子注入效果.进一步研究表明,等离子体离子注入后,在不锈铜基体表层形成了Cr2O3以及CrN,FeN等硬质相,因此处理后的试件耐摩擦、磨损和耐腐蚀性能得到了较大提高.同时研究显示,射频脉冲宽度或射频与高压相位的改变对摩擦系数影响不大.     

Improved electrical characteristics of high-k gated MOS devices by nitrogen incorporation with plasma immersion ion implantation (PIII)

High-k gate dielectric process is the key technology for nano-scale MOS device. A nitridation treatment on silicon surface is promising for characteristic improvement on high-k dielectric. It is found in this work that the electrical characteristics of high-k gated MOS devices can be improved by a nitridation treatment at silicon surface using plasma immersion ion implantation (PIII) at low ion energy and with a short implantation time. A shallow nitrogen profile at Si surface is known to be favorable for further enhancement of device properties.     

Selective silicon epitaxy by photo-chemical vapor deposition at a very low temperature of 160°C

We have grown epitaxial Si films by the photo-chemical vapor deposition (photo-CVD) technique with SiH₄ and H₂ at a very low-temperature of 160°C. Epitaxial films were grown on silicon substrates, while amorphous-like films were deposited on glass substrates. Furthermore, it was found from the atomic hydrogen etching which was produced by photo-dissociation of hydrogen that the etching rate of amorphous silicon was much higher than that of crystal silicon. By using these selectively, we have demonstrated selective epitaxial growth of silicon by the photo-CVD technique followed by the atomic hydrogen photo-etching. Furthermore, heavily phosphorus-doped silicon films (>1 × 10²¹ cm¹⁻³) were also selectively grown by this novel technique.