Characterization of flicker noise in GaN-based MODFET's at lowdrain bias

We report systematic characterizations of flicker noise in GaN based MODFET's. The devices were fabricated by MBE on (0001) basal plane sapphire substrates with an 800 Å AlN buffer layer grown at 800°C. Flicker noise was measured across the channel of the devices from room temperature to about 130 K. The voltage noise power spectra, S _V(f), were found to be proportional to 1/f^γ. The frequency exponent, γ, of S_V(f) exhibits systematic dependencies on the device temperature as well as the gate bias, V_G . The variation of the noise power spectra as a function of the drain voltage, V_D, and the gate bias, V_G, were studied in detail and were found to vary as V_D²/(V _G-V_T)^β where β changes with temperature from about 2.1 at room temperature to about 0.9 at 130 K. Analyses of the data show that the noise originated from the thermal activation of carriers to the localized states at the AlGaN/GaN heterointerface in the channel area. The data suggested that the trapping and detrapping of carriers did not lead to fluctuations in the carrier concentration as postulated in the McWhorter's model. However, more work is needed to determine if surface mobility fluctuations played a key role in the 1/f noise     

Spatial retardation of carrier heating in scaled 0.1-μmn-MOSFET's using Monte Carlo simulations

A comprehensive Monte Carlo simulator is employed to investigate nonlocal carrier transport in 0.1 μm n-MOSFET's under low-voltage stress. Specifically, the role of electron-electron (e-e) interactions on hot electron injection is explored for two emerging device designs biased at a drain voltage V_d considerably less than the Si/SiO₂ injection barrier height φ_b. Simulation of both devices reveal that 1) although qV_d<φ_b, carriers can obtain energies greater than φ_b, and 2) the peak for electron injection is displaced approximately 20 nm beyond the peak in the parallel channel electric field. These phenomena constitute a spatial retardation of carrier heating that is strongly influenced by e-e interactions near the drain edge. (Virtually no injection is observed in our simulations when e-e scattering is not considered.) Simulations also show that an aggressive design based on larger dopant atoms, steeper doping gradients, and a self-aligned junction counter-doping process produces a higher peak in the channel electric field, a hotter carrier energy distribution, and a greater total electron injection rate into the oxide when compared to a more conventionally-doped design. The impact of spatially retarded carrier heating on hot-electron-induced device degradation is further examined by coupling an interface state distribution obtained from Monte Carlo simulations with a drift-diffusion simulator. Because of retarded carrier heating, the interface states are mainly generated further over the drain region where interface charge produces minimal degradation. Thus, surprisingly, both 0.1 μm n-MOSFET designs exhibit comparable drain current degradation rates     

杂质浓度对槽栅PMOSFET抗热载流子特性的影响

基于流体动力学能量输运模型 ,利用二维仿真软件 Medici研究了深亚微米槽栅 PMOS器件衬底和沟道掺杂浓度对器件抗热载流子特性的影响 ,并从器件内部物理机理上对研究结果进行了解释。研究发现 ,随着沟道杂质浓度的提高 ,器件的抗热载流子能力增强 ;而随着衬底掺杂浓度的提高 ,器件的抗热载流子性能降低。这主要是因为这些结构参数影响了电场在槽栅 MOS器件内的分布和拐角效应 ,从而影响了载流子的运动并使器件的热载流子效应发生变化     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Threshold voltage, field effect mobility, and gate-to-channelcapacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V_t allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C_gc-V_GS characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C_gc characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C_gc curve can be related to the effective carrier transit time determined using the V_GS dependent field effect mobility     

体效应对超深亚微米SOI器件总剂量效应的影响

研究体偏置效应对超深亚微米绝缘体上硅（SOI,Silicon-on-insulator）器件总剂量效应的影响.在TG偏置下,辐照130nm PD（部分耗尽,partially depleted）SOI NMOSFET（N型金属-氧化物半导体场效应晶体管,n-type Metal-Oxide-Semiconductor Field-Effect Transistor）器件,监测辐照前后在不同体偏压下器件的电学参数.短沟道器件受到总剂量辐照影响更敏感,且宽长比越大,辐射导致的器件损伤亦更大.在辐射一定剂量后,部分耗尽器件将转变为全耗尽器件,并且可以观察到辐射诱导的耦合效应.对于10μm/0.35μm的器件,辐照后出现了明显的阈值电压漂移和大的泄漏电流.辐照前体偏压为负时的转移特性曲线相比于体电压为零时发生了正向漂移.当体电压Vb=-1.1V时部分耗尽器件变为全耗尽器件,|Vb|的继续增加无法导致耗尽区宽度的继续增加,说明体区负偏压已经无法实现耗尽区宽度的调制,因此器件的转移特性曲线也没有出现类似辐照前的正向漂移.     

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Forward body biasing is a promising approach for realizing optimum threshold-voltage (V _TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X _DEP) in the channel region, it reduces V _TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X _DEP ) at low V _TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |VF| should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.     

Optimization and realization of sub-100-nm channel length singlehalo p-MOSFETs

Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle V_T adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes     

Precise modeling of hot carrier gate current in short-channelMOSFET's

A powerful model which considers the fact that the values of the channel and carrier temperatures T and T_c vary with position in the bulk and channel is considered. It reveals that the energy distribution of hot carriers deviates from the well-known Maxwellian distribution by a small but nonnegligible perturbation and evaluates the dependence of this deviation of the device technology, geometry, and biasing conditions. The model helps to remove important discrepancies between the old hot-carrier models and measurements     

At-Bias Extraction of Access Parasitic Resistances in AlGaN/GaN HEMTs: Impact on Device Linearity and Channel Electron Velocity

AlGaN/GaN high-electron mobility transistor "hot" parasitic source and drain resistances R_S,D are determined under operating biases through wideband S-parameter measurements, without the use of "ColdFET" biasing conditions. Both R_S and R_D are found to increase dramatically over ColdFET values, both for biases approaching threshold and for open-channel conditions. Parasitic resistance values have a significant effect on the extracted small-signal equivalent circuit model elements, as well as on the apparent device linearity. The bias dependence of access resistances modifies the understanding of the transistor physical operation: A revised delay time analysis accounting for the bias dependence of parasitic resistances shows that the effective average electron velocity in the AlGaN/GaN two-dimensional electron-gas channel is approximately equal to 1.9 times 10⁷ cm/s. This new value of channel velocity is also consistent with the C_GS/g_MO ratio obtained when the bias dependence of R_S and R_D is accounted for during the extraction of the transistor small-signal equivalent circuit model     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET''''s

Grooved gate structure Metal-Oxide-Semiconductor (MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region, for it can suppress hot carrier effect and short channel effect deeply. Based on the hydrodynamic energy transport model, using two-dimensional device simulator Medici, the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel MOSFET's is studied and compared with that of counterpart conventional planar device in this paper. The examined structure parameters include negative junction depth, concave corner and effective channel length. Simulation results show that grooved gate device can suppress hot carrier effect deeply even in deep sub-micron region. The studies also indicate that hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device. With the increase of concave corner, the hot carrier effect in grooved gate MOSFET decreases sharply, and with the redu     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应 (HCE)进行了研究 .还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系 .在分析热载流子失效机理的基础上 ,讨论了热载流子效应对电路性能的影响 .提出影响晶体管热载流子效应的因素有 :晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置 .通过对这些失效因素的研究并通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化 .     

STUDY ON THE RELATION BETWEEN STRUCTURE AND HOT CARRIER EFFECT IMMUNITY FOR DEEP SUB-MICRON GROOVED GATE NMOSFET’s

Grooved gate structure Metal-Oxide-Semiconductor(MOS) device is considered as the most promising candidate used in deep and super-deep sub-micron region,for it can suppress hot carrier effect and short channel effect deeply.Based on the hydrodynamic energy transoprt model,using two-dimensional device simulator Medici,the relation between structure parameters and hot carrier effect immunity for deep-sub-micron N-channel Mosfet‘s is studied and compared with that of counterpart conventional planar device in this paper.The examined structure parameters include negative junction depth,conventinal planar device in this paper.The examined structure parameters include negative junction depth,concave corner and effective channel length.Simulation results show that grooved gate device can suppress hot carrier effect is strongly influenced by the concave corner and channel length for grooved gate device.With the increase of concave corner,the hot carrier effect in groovd gate MOSFET decreases sharply,and with the reducing of effective channel length,the hot carrier effect becomes large.     

A model for low frequency excess noise in Si-JFETs at low bias

Spectral analyses of the fluctuating drain-source voltages in n- and p-channel Si-JFETs at low bias conditions revealed generation-recombination (G-R) noise over a temperature range of 150–300 K in both types of devices. The corner frequencies f_C and the low frequency plateau values of the Lorentzian spectra were used to study the nature of the noise. In the n-channel device, f_C was strongly temperature dependent; an activation energy, E_C − E_T, of approximately 0.36 eV was obtained from the Arrhenius plot. For the p-channel device, a much higher corner frequency of 20–30 kHz was measured. Based on the experimental results we are led to consider a model for low frequency noise in JFETs that accounts for fluctuations in the channel thickness, and the correlated fluctuations in the number and the mobility of carriers. The relative significance of the three noise mechanisms was found to depend strongly on temperature, doping concentrations, device dimensions, and the energy level of the recombination centers.     

Investigation of broad-band quantum-well infrared photodetectorsfor 8-14-μm detection

Typical quantum-well infrared photodetectors (QWIPs) exhibit a rather narrow spectral bandwidth of 1-2 μm. For certain applications, such as spectroscopy, sensing a broader range of infrared radiation is highly desirable. In this paper, we report the design of four broad-band QWIPs (BB-QWIPs) sensitive over the 8-14-μm spectral range. Two n-type BB-QWIPs, consisting of three and four quantum wells of different thickness and/or composition in a unit cell which is then repeated 20 times to create the BB-QWIP structure, are demonstrated. The three-well n-type In_xGa_1-xAs-Al_yGa_1-yAs BB-QWIP was designed to have a response peak at 10 μm, with a full-width at half-maximum (FWHM) bandwidth that varies with the applied bias. A maximum bandwidth of Δλ/λ_p=21% was obtained for this device at V_b=-2 V. The four-well n-type In_xGa_1-xAs-GaAs BB-QWIP not only exhibits a large responsivity of 2.31 A/W at 10.3 μm and V_b=+4.5 V, but also achieves a bandwidth of Δλ/λ_p=29% that is broader than the three-well device. In addition, two p-type In _xGa_1-xAs-GaAs BB-QWIPs with variable well thickness and composition, sensitive in the 7-14-μm spectral range, are also demonstrated. The variable composition p-type BB-QWIP has a large FWHM bandwidth of Δλ/λ_p=48% at T=40 K and V_b=-1.5 V. The variable thickness p-type BB-QWIP was found to have an even broader FWHM bandwidth of Δλ/λ _p=63% at T=40 K and V_b=1.1 V, with a corresponding peak responsivity of 25 mA/W at 10.2 μm. The results show that a broader and flatter spectral bandwidth was obtained in both p-type BB-QWIP's than in the n-type BS-QWIP's under similar operating conditions     

Bias dependence of high-frequency noise in heterojunction bipolar transistors

Hawkins' isothermal model developed to study noise in bipolar junction transistors (BJTs) is modified to investigate bias-dependent noise in heterojunction bipolar transistors (HBTs) by incorporating thermal effects. It is shown that the inclusion of thermal effects into the high-frequency noise model of HBTs is necessary as the temperature of the device may become very different from the ambient temperature, especially at high bias current. Calculation of the noise figure by including the thermal effect shows that the isothermal calculation may underestimate the noise figure at high bias current. It is observed that noise at low bias is ideality factor n dependent whereas high bias noise is insensitive to the variation of n. Moreover, the common base current gain plays a major role in the calculation of the minimum noise figure. The excellent fit obtained between the theoretical calculation and the measured data are attributed to the inclusion of the bias-dependent junction heating as well as C/sub De/ and C/sub bc/ into the present calculation.     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Double-Recessed High-Frequency AlInGaN/InGaN/GaN Metal–Oxide Double Heterostructure Field-Effect Transistors

We demonstrate a low-threshold AlInGaN/InGaN/GaN metal-oxide semiconductor double heterostructure field-effect transistor (MOS-DHFET) for high-frequency operation. A combination of an InGaN channel (for carrier confinement), a DRE process, and a new digital-oxide-deposition technique helped us to achieve MOS-DHFET devices with extremely low subthreshold leakage currents. This reduction in output conductance (short channel effect) resulted in a high cutoff gain frequency f_T of about 65 GHz and a current gain frequency f _max of 94 GHz. The devices exhibited high drain-currents of 1.3 A/mm and delivered RF powers of 3.1 W/mm at 26 GHz with a 35 V drain bias.     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

Noise figure of UHF transistors as a function of frequency and bias conditions

It is shown that the observed values of the minimum noise figureF_{min}of UHF transistors in common base connection can be explained in terms of the device parameter(1-alpha_{dc}) r_{b'b}/R_{e0}and fαfor frequencies up to 1000 MHz. An interesting collector saturation effect is observed that gives a strong increase in UHF noise figure at high currents. Many features of the dependance ofF_{min}on operating conditions can be explained by this effect. The current dependence ofF_{min}for large values of |VCB| and high currents suggests a distribution in diffusion times through the base region. At intermediate frequencies, the noise figure increases with increasing collector bias |VCB| due to an increase inr_{b'b}, which in turn is caused by the dependence of the base width on |VCB|.