Extensible supply voltage control mechanism for low power array structure design

A novel supply voltage switching control mechanism, called D-logic, for reducing power dissipation of array structures is presented. With this D-logic mechanism, the supply voltage levels are successively activated by external clock signal in the direction of signal propagation, which eliminates power dissipated by the glitches. The mechanism is easily incorporated with minimal circuit change in the existing array structure, and the speed of the array structure can be maintained. We have reduced the energy consumption of the multipliers and CORDICs as much as 50% with the proposed D-logic circuitry.     

A systolic array realization of the adaptive decision feedback equalizer

This paper presents a systolic array architecture for the adaptive decision feedback equalizer. The design is based on an algebra developed earlier by Kung and Lin (Proceedings of the Conference of Elliptic Problem Solvers, Monterey, CA, January 1983; Research Report CMU-CS-84-100, Department of Computer Science, Carnegie-Mellon University, Pittsburgh, PA, April 1983.) and is largely made up of two basic processing cells that are computationally equivalent and simple to realize. To maintain accuracy of the algorithm, the array needs to be operated by a clock with a speed twice of that the input. The increase in clock speed can, however, be exploited to reduce the total number of adders and multipliers by about 50%.     

基于FPGA的高阶FIR抽取滤波器有效实现结构

针对高阶FIR抽取滤波器直接型结构和多相滤波结构中存在乘法器资源使用较多,导致实际系统实现困难的问题,提出了一种适合FPGA实现的高效多相结构。该结构采用分时复用技术,通过提高FPGA工作时钟频率,对降采样后的滤波路数和每一路FIR滤波器中乘积和操作均复用一个乘法器,从而大幅节约了FPGA中乘法器资源的使用。结果表明,针对4 096阶滤波器和降采样率为512的实际抽取滤波器系统,只需要8个乘法器,且在Xilinx公司Virtex IV芯片上能稳定工作在204.8 MHz的时钟频率上。     

Modified Booth Multipliers With a Regular Partial Product Array

The conventional modified Booth encoding (MBE) generates an irregular partial product array because of the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple approach is proposed to generate a regular partial product array with fewer partial product rows and negligible overhead, thereby lowering the complexity of partial product reduction and reducing the area, delay, and power of MBE multipliers. The proposed approach can also be utilized to regularize the partial product array of posttruncated MBE multipliers. Implementation results demonstrate that the proposed MBE multipliers with a regular partial product array really achieve significant improvement in area, delay, and power consumption when compared with conventional MBE multipliers.      

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm

We propose a radix-4 modular multiplication algorithm based on Montgomery's algorithm, and a fast radix-4 modular exponentiation algorithm for Rivest, Shamir, and Adleman (RSA) public-key cryptosystem. By modifying Booth's algorithm, a radix-4 cellular-array modular multiplier has been designed and simulated. The radix-4 modular multiplier can be used to implement the RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than a direct radix-2 implementation of Montgomery's algorithm. The time to calculate a modular exponentiation is about n/sup 2/ clock cycles, where n is the word length, and the clock cycle is roughly the delay time of a full adder. The utilization of the array multiplier is 100% when we interleave consecutive exponentiations. Locality, regularity, and modularity make the proposed architecture suitable for very large scale integration implementation. High-radix modular-array multipliers are also discussed, at both the bit level and digit level. Our analysis shows that, in terms of area-time product, the radix-4 modular multiplier is the best choice.     

少模光纤通信频域均衡中的大点数FFT设计

为了减小频域均衡系统电路实现的功耗和面积,满足长距离少模光纤通信对均衡器的要求,对关键环节快速傅里叶变换(FFT)电路的实现进行了研究,采用2维分解算法将大点数的FFT运算转换为小点数FFT处理器的设计,降低了硬件复杂度。设计了基于现场可编程门阵列的高速蝶形运算核,实现了16384点FFT的2维R22SDF结构,提高存储器的资源利用率,减少了复数乘法器的使用;进行了理论分析和实验验证,取得了不同时钟频率下的电路结构占用资源的数据。结果表明,FFT运算器的正确性得到验证,该FFT运算器能够适应少模光纤通信系统中优化频域均衡电路结构的要求,能够实现200MHz数据传输速度的频域均衡实时处理。     

Digital Frequency Multipliers Using Multisection Two-Strip Coupled Line

This paper describes new networks which acts as digital frequency multipliers such as doubler, tripler, and so on for input clock frequency. The networks consist of cascaded sections of uniform lossless commensurate coupled-transmission-lines and three resistors of II-structure, and the proposed multipliers are quite new in the sense of being built without using active or nonlinear circuit elements. The theoretical and experimental results for a coupled-line digital frequency doubler are compared and found to be in good agreement.     

一种开关移位式32位乘法器的设计

乘法器在CPU的ALU设计中是很重要,也是较为复杂的一部分,它占据大的面积和较长的延时.根据系统不同的要求,我们可以设计出不同的乘法器.本文是在系统时钟要求和面积两方的限制下做了折衷,提出了一种基于开关和移位工作方式的多时钟周期乘法器的设计.最后用DC进行综合,并经VCS仿真得到结果与SYNOPSYS公司design_ware里的乘法器进行比较,指出其优缺点.     

Cellular logical array for obtaining the square of a binary number

An array of logical networks is described, the function of which is to obtain the square of a binary number. The array is faster than other general multipliers and uses considerably fewer cells than these arrays.     

Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks

In this paper, techniques for efficient implementation of field-programmable gate-array (FPGA)-based wave-pipelined (WP) multipliers, accumulators, and filters are presented. A comparison of the performance of WP and pipelined systems has been made. Major contributions of this paper are development of an on-chip clock generation scheme which permits finer tuning of the frequency, a synthesis technique that reduces the area and latency by 25%, a placement utility that results in 10%–40% increase in speed and proposal of an interleaving scheme for filters that reduces the number of multipliers required by 50%. WP multipliers of size 2$times$6 and the filters using them are found to be 11% faster and require lower power than those using pipelined multipliers. Filters with higher order WP multipliers also operate with lower power at the cost of speed. The delay-register products of such filters are found to be about 60% lower than those using the pipelined multipliers. The paper also outlines applications of these techniques for the Spartan II FPGAs and a self-tuning scheme for optimizing the speed.     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

In this paper, a delay-locked loop (DLL)-based clock generator is presented. Although a DLL-based clock generator requires a clean reference signal, it has several inherent advantages over conventional phase-locked-loop-based clock generators, i.e., no jitter accumulation, fast locking, stable loop operation, and easy integration of the loop filter. We propose a phase detector with a reset circuitry and a new frequency multiplier to overcome the limited locking range and frequency multiplication problems of the conventional DLL-based system. Fabricated in a 0.35-/spl mu/m CMOS process, our DLL-based clock generator occupies 0.07 mm/sup 2/ of area and consumes 42.9 mW of power. It operates in the frequency range of 120 MHz-1.1 GHz and has a measured cycle-to-cycle jitter of /spl plusmn/7.28 ps at 1 GHz. The die area, peak-to-peak, and r.m.s. jitter are the smallest compared to those of reported high-frequency clock multipliers.     

Array multiplication scheme using (p, 2) counters and pre-addition

The authors propose a pre-add counter scheme that provides for common operand lengths and a speedup, measured in terms of CSAs, by a factor of up to 9 over CSA array multipliers and by a factor up to 2 over parallel multipliers using Lim counters. Furthermore, it permits efficient mapping in VLSI implementations     

基于FPGA的数字乘法器性能比较

详细描述了四种基本的FPGA数字乘法器设计方法即阵列法、查找表法、移位相加法、Booth法的原理和实现过程.以4×4和16×16数字乘法器的设计为例,通过在AlteraFPGA芯片上的仿真与综合,给出了这四种数字乘法器的运算速度和占用逻辑资源情况.结果表明随着位宽的变化,各方法的相对效果会有变化,对于具有较宽数据位的乘...     

Quad-level bit-stream adders and multipliers with efficient FPGA implementation

Novel adder and multiplier circuits for bit-stream signal processing customised for quad-level sigma-delta modulated signals are proposed. Compared with existing sorter-based quad-level sigma-delta adders and multipliers, the proposed implementation is more resource-efficient (>76% hardware savings) and faster (>93% higher clock frequency) when realised on state-of-the-art FPGA architecture featuring six- input look-up tables.     

High performance low power array multiplier using temporal tiling

Digital multipliers are a major source power dissipation in digital signal processors. Array architecture is a popular technique to implement these multipliers due to its regular compact structure. High power dissipation in these structures is mainly due to the switching of a large number of gates during multiplication. In addition, much power is also dissipated due to a large number of spurious transitions on internal nodes. Timing analysis of a full adder, which is a basic building block in array multipliers, has resulted in a different array connection pattern that reduces power dissipation due to the spurious transition activity. Furthermore, this connection pattern also improves the multiplier throughput. This array pattern is based on creating a compact tiled structure, wherein the shape of a tile represents the delay through that tile. That is, a compact structure created using these tiles is nothing but a structure with high throughput. Such a temporal tiling technique can also be applied to other digital circuits. Based on our simulation studies, a temporally tiled array multiplier achieves 50% and 35% improvements in delay and power dissipation compared to a conventional array multiplier. Improvement in delay can be traded for power using voltage reduction techniques     

Novel systolic array realisation of allpass digital filters for high speed applications

A novel systolic array realisation of a general allpass digital filter of any arbitrary order suitable for high speed delayed N-path recursive digital filtering applications is presented. The proposed systolic array is a purely systolic (not semisystolic) design which is also canonic in the number of multipliers, modulator in having one type of basic cell, and has nearest neighbour interconnections.<>     

二维DCT快速算法及FPGA实现

本文提出了一种二维OCT快速算法的FPGA实现结构,采用行列快速算法将二维DCT分解成两个一维DCT实现,其中一维DCT借鉴Loeffler DCT算法,采用并行的流水线结构,提高电路的数据吞吐率和运算速度,通过系数矩阵的简化和蝶形运算结构的等价减少乘法器的消耗,一维DCT核消耗16个乘法器.转置RAM采用8片双口RAM,一个时钟可以完成 8个数据读写.实验结果验证了二维DCT核设计的正确性,该电路结构消耗资源少,布线简单,功耗小,适合图像的实时处理.     

Highly efficient, limited range multipliers for LUT-based FPGA architectures

A novel design technique for deriving highly efficient multipliers that operate on a limited range of multiplier values is presented. Using the technique, Xilinx Virtex field programmable gate array (FPGA) implementations for a discrete cosine transform and poly-phase filter were derived with area reductions of 31%-70% and speed increases of 5%-35% when compared to designs using general-purpose multipliers. The technique gives superior results over other fixed coefficient methods and is applicable to a range of FPGA technologies.