超薄SiO_2膜电子隧穿及低场传输电流的温度关系

在Ｎ－Ｓｉ〈１００〉衬底制作了１０ｎｍ超薄ＳｉＯ２作介质膜的ＭＯＳ结构．研究了温度从１００～４５０Ｋ电子从Ｓｉ界面积累层Ｆ－Ｎ隧穿超薄ＳｉＯ２的Ｉ－Ｖ特性及低场传输电流随温度的变化关系．研究结果表明：在较低的温度下，电流与温度基本无关；而在较高的温度下，电流随温度指数增加．为从理论上解释这些实验结果，认为在Ｆ－Ｎ隧穿电场范围，电流密度Ｊ１∝Ｆ２ｅｘｐ（－β／Ｆ），而在低场范围电流Ｊ＝Ｊ０＋Ｊ２，Ｊ２∝Ｆｅｘｐ（－Φ２／ｋＴ）．Ｊ０为低场漏电流．Ｊ１从实验数据可以求出，电子从Ｎ型Ｓｉ〈１００〉隧穿超薄ＳｉＯ     

MOS结构二氧化硅层中电子热化与击穿

本文讨论了ＭＯＳ结构的二氧化硅膜中电子热化现象的实验证据，表明：当氧化物电场≥５ＭＶ／ｃｍ时，注入到二氧化硅膜中的电子逐渐地热化，热电子在二氧化硅膜中产生新的电荷陷阱中心，当电荷陷阱中心的密度增大到一定程度时，导致二氧化硅膜的电击穿。     

MOS结构SiO2膜陷阱化动力学

本文建立了在高电场Ｆ－Ｎ隧穿注入条件下，ＭＯＳ结构ＳｉＯ膜中包含陷阱产生现象的陷阱化动力学方程。由这些方程导出若干结果；并这些结果，提出了确定ＳｉＯ膜内陷阱特性参量的分析方法。也简单讨论了二氧化硅膜内几各不同类型陷阱。     

脉冲激光沉积铌酸锶钡铁电薄膜及其性能表征

利用脉冲激光沉积（ＰＬＤ）技术在ＭｇＯ、ＬＳＣＯ／ＭｇＯ衬底上在位制备了铌酸锶钡（ＳＢＮ）铁电薄膜,发现ＳＢＮ薄膜在ＭｇＯ、ＬＳＣＯ／ＭｇＯ衬底上均呈（００１）择优取向。用扫描电子显微镜（ＳＥＭ）和原子力显微镜（ＡＦＭ）表明ＳＢＮ薄膜的晶粒细小致密,铁电微畴尺寸约为２００ｎｍ。ＳＢＮ薄膜的剩余极化强度为１８．６μＣ／ｃｍ２,矫顽场为２２．３ｋＶ／ｃｍ。     

大面积水听器用0-3型压电复合材料的制备

以钛酸铝（ＰＴ）和Ｆ２４「Ｐ（ＶＤＦ－ＴＦＥ）」为原材料，利用热轧法和旋转电晕放电极化方法制备出面积达３７５ｃｍ＾２，厚为首领μｍ的大面积０－３型ＰＴ／Ｐ（ＶＤＦ－ＴＦＥ）压电复合材料。其压电应变系数为３２ｐＣ／Ｎ，静水压压电系这到７８２．６ｍＶ．ｍ／Ｎ，并对其温度和压力稳定性进行了分析测试。     

SOI／SDB COMS环形振荡器的研究

本文主要研究了硅片直接键合技术制备ＳＯＩ材料，并在此材料上采用全离子注入硅栅工艺制造了１μｍ沟道ＣＭＯＳ环形振荡器。由于ＳＯＩ。ＳＤＢ中的硅膜保持着本体硅的性质，故所得陪管的特性比较好，（迁移率：ＮＭＯＳ为６８０ｃｍ２／Ｖ·ｓ，ＰＭＯＳ为３７０ｃｍ２／Ｖ·ｓ，跨导：ＮＭＯＳ为３８ｍＳ，ＰＭＯＳ为２５ｍＳ）。但发现ＭＯＳ管具有“Ｋｉｎｋ”效应，随着硅膜厚度的减小，“Ｋｉｎｋ”效应有所抑制。实验所得ＣＭＯＳ１９级环形振荡器的单级延时为０．７９ｎｓ，由此可见，ＳＯＩ／ＳＤＢ材料在ＶＬＳＩ中将有很大的发展前景     

注入损伤及其对隧穿的影响

注入损伤及其对隧穿的影响＝Ｉｍｐｌａｎｔａ－ｔｉｏｎｄａｍａｇｅａｎｄｉｔｓｅｆｆｅｃｔｏｎｃｈａｎｎｅｌｌｉｎｇ［刊，英］／Ｂｅｎ－ｎｅｔｔ．Ｄ．Ｊ．…Ｍｉｃｒｏｅｌｅｃｔｒｏｎ．Ｊ．－１９９３．２４（７）．－８１１～８１７用隧穿效应模拟硅中的注入...     

用强流金属离子源研究Ti－Si化合物的形成

利用金属蒸汽真空弧（ＭＥＶＶＡ）离子源引出强流Ｔｉ离子注入单晶硅，当ＭＥＶＶＡ源引出电压为４０ｋＶ，束流密度达到１００μＡ／ｃｍ２，Ｔｉ离子剂量为５×１０１７／ｃｍ２，Ｔｉ离子注入单晶硅可得到Ｃ５４－ＴｉＳｉ２的注入层，且薄层电阻低于３．０Ω／□．本文用束流热效应讨论了形成硅化物的机理．     

6H—SiC反型沟道和掩埋沟道MOS器件的特性

介绍了在宽禁带半导体６Ｈ－ＳｉＣ材料上制作的反型沟道和掩埋沟道栅控二极管及ＭＯＳＦＥＴ。器件的制作采用了热氧化和离子注入技术。因为６Ｈ－ＳｉＣ禁带宽度为３ｅＶ，用ＭＯＳ电容很难测量表面态，故利用栅控二极管在室温条件下来测量表面态。反型沟道器件中电子有效迁移率为２０ｃｍ＾２／Ｖ．ｓ，而掩埋沟道ＭＯＳＦＥＴ沟道中的体电子迁移率为１８０ｃｍ＾２／Ｖ．ｓ，掩埋沟道晶体管是第一只ＳｉＣ离子注入沟道器件，也是     

超强圆极化激光脉冲中氢原子阈上电离谱

由于激光技术的发展，在实验室中人们已可使聚焦激光束斑的光强达到１０~２０Ｗ／ｃｍ２．这个光强中激光电场比氢原子基态电子所感受到的库仑电场高出数百倍．这是目前人们在实验室中能获得的最高强度的电场．而光强为１０~２２Ｗ／ｃｍ~２的强激光，预计会在今后的一二年中出现．超强短脉冲激光器的发展，使人们开创了激光与物质相互作用研究的新领域．在这个强场与物质相互作用的新领域，实验已发现一系列有潜在应用前景的新现象．用超强激光（＞１０~１９Ｖ／ｃｍ~２）辐照固体靶的实验中，ＭｅＶ的超热电子的发现就是其中一例．快点火…     

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO₂) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n⁺-polySi) gate. The analysis utilizes the measured gate current density J_G at high oxide fields E_ox in 5.4 to 12 nm thick SiO₂ films between 25 and 300℃. The leakage current measured up to 300℃ was due to Fowler–Nordheim (FN) tunneling of electrons from the accumulated n⁺-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO₂ conduction band (CB). It was observed that PF emission current I_PF dominates FN electron tunneling current I_FN at oxide electric fields E_ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO₂ films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide–semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant     

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (T_bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with T_bo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor     

GaN基肖特基势垒二极管的漏电流传输与退化机制

通过比较反向偏压下AlGaN/GaN异质结肖特基势垒二极管(SBD)和GaN SBD的电流特性、电场分布和光发射位置,研究了GaN基SBD的漏电流传输与退化机制。结果表明,AlGaN/GaN SBD退化前后漏电流均由Frenkel-Poole(FP)发射机制主导,而GaN SBD低场下为FP发射电流,高场下则为Fowler-Nordheim(FN)隧穿电流。电场模拟和光发射测试结果表明,引起退化的主要原因是高电场,由于结构不同,两种SBD的退化机制和退化位置并不相同。根据实验结果,提出了一种高场FN隧穿退化模型,该模型强调应力后三角势垒变薄导致FN隧穿增强是GaN SBD退化的内在机制。     

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 10¹² cm ^-2 in the upper part of the nc-Si film is reduced to 2.1 times 10¹² cm^-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

The analysis of leakage current in MIS Au/SiO2/n-GaAs at room temperature

The aim of this study is to determine the reverse-bias leakage current conduction mechanisms in Au/SiO₂/n-GaAs metal-insulator-semiconductor type Schottky contacts. Reverse-bias current-voltage measurements (I–V) were performed at room temperature. The using of leakage current values in SiO₂ at electric fields of 1.46–3.53 MV/cm, ln(J/E) vs. $\sqrt E $ graph showed good linearity. Rom this plot, dielectric constant of SiO₂ was calculated as 3.7 and this value is perfect agreement with 3.9 which is value of SiO₂ dielectric constant. This indicates, Poole-Frenkel type emission mechanism is dominant in this field region. On the other hand, electric fields between 0.06–0.73 and 0.79–1.45 MV/cm, dominant leakage current mechanisms were found as ohmic type conduction and space charge limited conduction, respectively.     

Stress-induced leakage current in p+ poly MOS capacitorswith poly-Si and poly-Si0.7Ge0.3 gatematerial

The gate bias polarity dependence of stress-induced leakage current (SILC) of PMOS capacitors with a p⁺ polycrystalline silicon (poly-Si) and polycrystalline Silicon-Germanium (poly-Si_0.7 Ge_0.3) gate on 5.6-nm thick gate oxides has been investigated. It is shown that the SILC characteristics are highly asymmetric with gate bias polarity. This asymmetric behavior is explained by the occurrence of a different injection mechanism for negative bias, compared to positive bias where Fowler-Nordheim (FN) tunneling is the main conduction mechanism. For gate injection, a larger oxide field is required to obtain the same tunneling current, which leads to reduced SILC at low fields. Moreover, at negative gate bias, the higher valence band position of poly-SiGe compared to poly-Si reduces the barrier height for tunneling to traps and hence leads to increased SILC. At positive gate bias, reduced SILC is observed for poly-SiGe gates compared to poly-Si gates. This is most likely due to a lower concentration of Boron in the dielectric in the case of poly-SiGe compared to poly-Si. This makes Boron-doped poly-SiGe a very interesting gate material for nonvolatile memory devices     

Investigation of the energy distribution of stress-induced oxide traps by numerical analysis of the TAT of HEs

This paper investigates by numerical modeling the results of substrate hot electron (SHE) injection experiments in virgin and stressed devices and the corresponding increase of the contribution of HEs to the gate current due to the stress-induced oxide traps. Experimental evidence of HE trap-assisted tunneling (HE TAT) is found after Fowler-Nordheim (FN) stress and SHE stress. An accurate physically based model developed to interpret the experimental results allowed us to study the energy distribution of generated oxide traps in the two different stress regimes. It is found that degradation in HE stress conditions and FN stress conditions cannot be explained by the same trap distribution. For a given stress-induced low field leakage current, a larger concentration of traps in the top part of the oxide band gap is needed to explain HE TAT after SHE stress than after FN stress. The range of trap energy where each technique is sensitive is also identified.     

Conduction mechanisms in thermal nitride and dry gate oxides grown on 4H-SiC

The charge conduction mechanisms in Metal-Oxide-Semiconductor (MOS) capacitors formed on n-type 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO₂) as gate dielectrics are analyzed. The possible conduction mechanisms have been identified in the whole measurement range. At high electric fields, the charge conduction is dominated by Fowler–Nordheim tunneling. In addition, trap assisted tunneling and ohmic type conduction are considered to explain the cause of leakages detected at intermediate and low oxide electric fields. Various electronic parameters are extracted. The oxide breakdown strengths are higher than 8 MV/cm. Fowler–Nordheim tunneling barrier height was found to be 2.74 eV for nitride oxides and 2.54 eV for dry oxides at high electric field regions and the trap energy level extracted using trap assisted tunneling emission model was estimated to be about 0.3 eV for both oxides. The possible contribution of the Poole–Frenkel effect to the conduction mechanism was also considered, and it was found that it does not play a dominant role.