Current directions in automatic test-pattern generation

Test development automation tools, which automate dozens of tasks essential for developing adequate tests, generally fall into four categories: design for testability (DFT), test pattern generation, pattern-grading, and test program development and debugging. The focus in the article is on automatic test-pattern-generation tools. Researchers have looked primarily at issues such as scalability, ability to handle various fault models, and how to extend the algorithms beyond Boolean domains to handle different abstraction levels. Their aims were to speed up test generation, reduce test sequence length, and minimize power consumption. As design trends move toward nanometer technology however, new ATPG problems are emerging. Current modeling and vector generation techniques must give way to new techniques that consider timing information during test generation, scale to larger designs, and can capture extreme design conditions. The authors describe current ATPG techniques and efforts to adapt ATPG technology to handle deep-submicron faults and to identify design errors and timing problems during design verification     

Failure diagnosis of structured VLSI

The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure. Diagnosis consists of simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel. The method is also suitable for signature-based random-pattern testing. The authors discuss diagnostic fault simulation, fault-list generation, relating faults to defects, diagnostic strategy, and random-pattern failures, and they report some experimental results to indicate the procedure's power     

面向HDL描述基于路径覆盖的模拟矢量自动生成方法研究

提出和实现了一种面向HDL描述基于路径覆盖的模拟矢量自动生成方法,该方法在约束生成时只考虑控制语句的条件表达式，可有效避免生成冗余约束；利用扩展的决策图模型解决了中间信号到初始输入的传播问题和信号依赖关系问题，以及处理各种HDL描述风格的问题；采用约束逻辑编程方法解决了由位、位向量和整型变量组成的约束系统的统一处理问题,实验结果表明该方法能加快模拟矢量生成速度，提高路径覆盖率．生成的模拟矢量也能用于低层次设计验证和故障模拟，加快了设计进度,将该方法的原型系统用于一个32位微处理器核RTL级验证，发现了RTL级设计描述中的错误．     

Transition Fault Simulation

Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.     

The reliability of approximate testability measures

Techniques for gauging the accuracy of approximate testability measures that estimate the random-pattern testability of gate-level faults in designs with combinational logic are considered. The measures examined are overall fault-exposure distribution, high coverage, and fault grading. Sampling techniques are compared with the Stafan and Protest approximate testability measures. For random-pattern testing, it is clear that state-of-the-art testability measures like Stafan and Protest do provide some information about the testability of single faults or complete designs, but this information is not accurate; in many areas of use they cannot compete with carefully chosen sampling techniques. The three techniques described here are applicable to testing strategies other than the random-pattern testing of stuck-at faults; they are equally useful in a weighted random-pattern testing environment, for example     

Desing and self-test for switched-current building blocks

This switched-current memory cell with a built-in self-test option serves as a building block for a range of analog functions. As an example application, the authors present a divide-by-two circuit for reference signal generation in algorithmic A/D converters. They also describe two self-test approaches for these building blocks and evaluate their effectiveness. The self-test functions are easy to apply, require very little overhead, and result in fault coverage up to 95% for shorts and 60% for open circuits. Analysis reveals that 100% testability may not be achievable in a cost-effective way for mixed-signal circuits     

一种高性能数字滤波器的ASIC设计方法与Matlab仿真验证

介绍一种用于高性能ΔΣ模数转换器的数字滤波器的设计方法,分析其频率特性和高通滤波特性,给出频率仿真结果.依靠Matlab软件的语言环境验证设计方法,编程实现数字滤波器的行为级仿真,这与其它数字滤波器的设计中利用Matlab信号处理工具箱中专门用于滤波器设计与分析的工具完全不同.按照这种设计思想实现的滤波器通过Matlab仿真获得了很好的性能.该方法适用于对硬件面积有严格要求的数字滤波模块的ASIC设计.     

Linking simulation with formal verification at a higher level

We use simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. Our technique verifies that a hardware design described at the RTL is a correct implementation of an algorithm-level, executable formal specification. We use a high-level formal specification as the basis for monitoring functional correctness, measuring simulation coverage, and generating test cases.     

A workstation approach to IC process and device design

IC designers are turning more and more to CAD tools to develop complex designs and to automate time-consuming tasks. Although there are a variety of integrated tools for many types of VLSI design, very few integrated systems have been built to address process and device design. Recognizing this need, researchers at MIT set out to define the requirements of a process and device design environment, implement a subset of these functions, and integrate the tools into a user-friendly design environment. As part of their work on creating a user-friendly environment, they developed the MASTIF workstation to provide graphic, window-oriented user interaction to process and device designers     

Formal methods for protocol testing: a detailed study

The authors present a detailed study of four formal methods (T-, U-, D-, and W-methods) for generating test sequences for protocols. Applications of these methods to the NBS Class 4 Transport Protocol are discussed. An estimation of fault coverage of four protocol-test-sequence generation techniques using Monte Carlo simulation is also presented. The ability of a test sequence to decide whether a protocol implementation conforms to its specification heavily relies on the range of faults that it can capture. Conformance is defined at two levels, namely, weak and strong conformance. This study shows that a test sequence produced by T-method has a poor fault detection capability, whereas test sequences produced by U-, D-, and W-methods have comparable (superior to that for T-method) fault coverage on several classes of randomly generated machines used in this study. Also, some problems with a straightforward application of the four protocol-test-sequence generation methods to real-world communication protocols are pointed out     

基于改进V-detector算法的转子故障识别方法研究

为了提高转子故障诊断识别准确率, 提出一种基于改进V-detector算法的转子故障辨识方法。首先对V-detector算法进行了改进, 该算法通过改变拒绝和接受假设检验的条件来减少无效检测器的产生进而提高算法的检测准确率; 然后将信号的谱熵值作为特征向量, 并根据转子故障类型将其划分为多个自体样本集, 用改进后V-detector算法训练出多个检测器集; 最后利用其设计出能够识别转子故障的分类器。仿真结果表明, 改进的V-detector算法能产生较少的检测器, 覆盖率由95%升高至99%时检测器数目无明显增加, 与原算法相比提高了故障的辨识精度。     

An integrated environment for teaching computer architecture

A major problem in teaching computer architecture and organization courses is how to help students make the cognitive leap that connects their theoretical knowledge with practical experience. Numerous researchers involved in computer architecture and organization education have tackled this problem, resulting in a variety of educational tools for computer system simulation. The tools differ greatly in scope, target architecture complexity, simulation level, and user interface. The available educational systems vary in how they handle digital system simulation. They usually offer tools for creating hardware component libraries, viewing simulation results, and conducting statistical analysis of system performance. Available systems range from sophisticated ones, for complex analysis, to simpler ones that are more readily understood by users, both instructors and students. Beyond system simulation, an educational system should support three key objectives. First, it must cover an extensive range of computer architecture and organization topics. Second, it should graphically depict a computer system, from the block level to the register-transfer level. Third, it must provide the means to follow system functions at the program, instruction, and clock cycle levels     

系统芯片IP核透明路径构建中的可测性分析

系统芯片的设计方法为测试技术带来新挑战。知识产权模块（IP核）测试访问机制成为测试复用的关键。构建IP核透明路径会对电路的故障覆盖率产生影响。基于门级透明路径的构建方法，通过分析插入电路的控制门和多路器的激活和传播条件，对路径构建对于IP核单固定型故障覆盖率的影响进行分析，给出可测性条件和故障覆盖率的计算公式，无需故障仿真即可估计构造透明路径后电路的故障覆盖率。通过故障仿真实验，证明该故障覆盖率的分析和计算方法是有效的。     

Design validation: comparing theoretical and empirical results ofdesign error modeling

To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results     

Using coverage to automate and improve test purpose based testing

Test purposes have been presented as a solution to avoid the state space explosion when selecting test cases from formal models. Although such techniques work very well with regard to the speed of the test derivation, they leave the tester with one important task that influences the quality of the overall testing process: test purposes have to be formulated manually. In this paper, we present an approach that assists a test engineer with test purpose design in two ways: it allows automatic generation of coverage based test suites and can be used to automatically exercise those aspects of the system that are missed by hand-crafted test purposes. We consider coverage of Lotos specifications, and show how labeled transition systems derived from such specifications have to be extended in order to allow the application of logical coverage criteria to Lotos specifications. We then show how existing tools can be used to efficiently derive test cases and suggest how to use the coverage information to minimize test suites while generating them.     

Simulating simulation-agnostic SysML models for enterprise information systems via DEVS

Systems Modeling Language (SysML) is used as the modeling infrastructure in systems engineering, especially for complex systems design, independently of the system domain. Simulation is a common method to perform system model verification, during the systems development process. However, simulation code generation and execution is not integrated within the system design activity, as it is facilitated by SysML. It is either conducted as an external activity, after system design, or it affects the system design environment and practices, according to specific simulators requirements.This paper presents how existing, simulation-agnostic SysML models from the domain of Enterprise Information System (EISs), can be transformed to executable simulation code and in addition how the simulation results can be incorporated into the source SysML model through the exploitation of Model Driven Architecture (MDA) principles and techniques. To this end, several tools and technologies are utilized, while the verification process is triggered and finalized via the system modeling environment. Adoption of MDA provides a solid, high-level infrastructure and tool availability to the proposed approach.     

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions’ architectures

Many cryptographic primitives that are used in cryptographic schemes and security protocols such as SET, PKI, IPSec and VPN's utilize hash functions - a special family of cryptographic algorithms. Hardware implementations of cryptographic hash functions provide high performance and increased security. However, potential faults during their normal operation cause significant problems in the authentication procedure. Hence, the on-time detection of errors is of great importance, especially when they are used in security-critical applications, such as military or space. In this paper, two Totally Self-Checking (TSC) designs are introduced for the two most-widely used hash functions: SHA-1 and SHA-256. To the best of authors’ knowledge, there is no previously published work presenting TSC hashing cores. The achieved fault coverage is 100% in the case of odd erroneous bits. The same coverage is achieved for even erroneous bits, if they are appropriately spread. Additionally, experimental results in terms of frequency, area, throughput, and power consumption are provided. Compared to the corresponding Duplicated with Checking (DWC) architectures, the proposed TSC-based designs are more efficient in terms of area, throughput/area, and power consumption. Specifically, the introduced TSC SHA-1 and SHA-256 cores are more efficient by 16.1% and 20.8% in terms of area and by 17.7% and 23.3% in terms of throughput/area, respectively. Also, compared to the corresponding DWC architectures, the proposed TSC-based designs are on average almost 20% more efficient in terms of power consumption.     

Parallel qualitative simulation

Qualitative simulation is a rather new and challenging simulation paradigm. Its major strength is the prediction of all physically possible behaviors of a system given only weak and incomplete information about it. This strength is exploited more and more in applications like design, monitoring and fault diagnosis. However, the poor performance of current qualitative simulators complicates or even prevents their application in technical environments. This paper presents the development of a special-purpose computer architecture for the bestknown qualitative simulator QSIM. Two design methods are applied to improve the performance. Complex functions are parallelized and mapped onto a multiprocessor system. Less complex functions are accelerated by software to hardware migration; they are executed on specialized coprocessors.