Resistive switching induced by metallic filaments formation through poly(3,4-ethylene-dioxythiophene):poly(styrenesulfonate)

We report the design and fabrication of Al/poly(3,4-ethylene-dioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/Cu resistive memory devices that utilize the Cu redox reaction and conformational features of PEDOT:PSS to achieve resistive switching. The top Cu electrode acts as the source of the redox ions that are injected through the PEDOT:PSS layer during the forming process. The Cu filament is confirmed directly using the cross-sectional images of transmission electron microscopy and energy-dispersive X-ray spectroscopy. The resultant resistive memory devices can operate over a small voltage range, i.e., the switching-on threshold voltage is less than 1.5 V and the absolute value of the switching-off threshold voltage is less than 1.0 V. The on/off current ratio is as large as 1 × 10(4) and the two different resistance states can be maintained over 10(6) s. Moreover, the devices present good thermal stability that the resistive switching can be observed even at temperature up to 160 °C, at which the oxidation of the Cu top electrode is the failure factor. Furthermore, the cause of failure for Al/PEDOT:PSS/Cu memory devices at higher temperature is confirmed to be the oxidation of Cu top electrode.     

The growth and characterization of ZnO/ZnTe core-shell nanowires and the electrical properties of ZnO/ZnTe core-shell nanowire field effect transistor

Vertically aligned ZnO/ZnTe core-shell nanowires were grown on a-plane sapphire substrate by using chemical vapor deposition with gold as catalyst for the growth of ZnO core and then followed by growing ZnTe shell using metal-organic chemical vapor deposition (MOCVD). Transmission electron microscope (TEM) and Raman scattering indicate that the core-shell nanostructures have good crystalline quality. Three-dimensional fluorescence images obtained by using laser scanning confocal microscope demonstrate that the nanowires have good optical properties. The core-shell nanowire was then fabricated into single nanowire field effect transistor by standard e-beam photolithography. Electrical measurements reveals that the p-type ZnO/ZnTe FET device has a turn on voltage of -1.65 V and the hole mobility is 13.3 cm2/V s.     

Controlling orientation of V(2)O(5) nanowires within micropatterns via microcontact printing combined with the gluing Langmuir-Blodgett technique

Previously, we suggested a facile method to transfer dioctadecyldimethylammonium bromide (DODAB)/V(2)O(5) nanowire hybrid patterns onto both hydrophobic and hydrophilic substrates via microcontact printing combined with the Langmuir-Blodgett (LB) technique (Park et al 2007 Nanotechnology 18 405301). Herein, we report on the delicate control of the orientation of V(2)O(5) nanowires within the micropatterns transferred via the gluing LB technique using a patterned polydimethylsilicate (PDMS) stamp. According to the orientation of the PDMS line patterns relative to the air-water interface, the aligned orientation of the nanowires, either parallel or perpendicular to the patterns, could be obtained and attributed to the moving direction of the water menisci formed between the PDMS stamp and water. In particular, addition of a small amount of ethanol in the subphase enhanced the dispersion of the DODAB at the air-water interface as well as the aggregation of V(2)O(5) nanowires, resulting in alignment of the V(2)O(5) nanowires via compression of the hybrid LB film by a barrier. Directional alignment of nanowires has potentially broad applications in the fabrication of aligned nanowire devices.     

High Performance Photoswitches Based on Flexible and Amorphous D–A Polymer Nanowires

A fluorene‐based donor–acceptor conjugated polymer is synthesized and the polymer nanowires are successfully prepared with high quality and large scale using a simple and practical template dipping method. These amorphous polymer nanowires are flexible and show excellent photoconductive properties with reliable reproducibility. The individual nanowire photoswitches exhibit a responsivity as high as 1700 mA W^?1 and an on/off ratio as high as 2000 under a light intensity of 5.76 mW cm^?2 and a driving voltage of 40 V.     

Fabrication of organic field effect transistor by directly grown poly(3 hexylthiophene) crystalline nanowires on carbon nanotube aligned array electrode

We fabricated organic field effect transistors (OFETs) by directly growing poly (3-hexylthiophne) (P3HT) crystalline nanowires on solution processed aligned array single walled carbon nanotubes (SWNT) interdigitated electrodes by exploiting strong π-π interaction for both efficient charge injection and transport. We also compared the device properties of OFETs using SWNT electrodes with control OFETs of P3HT nanowires deposited on gold electrodes. Electron transport measurements on 28 devices showed that, compared to the OFETs with gold electrodes, the OFETs with SWNT electrodes have better mobility and better current on-off ratio with a maximum of 0.13 cm(2)/(V s) and 3.1 × 10(5), respectively. The improved device characteristics with SWNT electrodes were also demonstrated by the improved charge injection and the absence of short channel effect, which was dominant in gold electrode OFETs. The enhancement of the device performance can be attributed to the improved interfacial contact between SWNT electrodes and the crystalline P3HT nanowires as well as the improved morphology of P3HT due to one-dimensional crystalline nanowire structure.     

Parallel arrays of Schottky barrier nanowire field effect transistors: Nanoscopic effects for macroscopic current output

We present novel Schottky barrier field effect transistors consisting of a parallel array of bottom-up grown silicon nanowires that are able to deliver high current outputs. Axial silicidation of the nanowires is used to create defined Schottky junctions leading to on/off current ratios of up to 10⁶. The device concept leverages the unique transport properties of nanoscale junctions to boost device performance for macroscopic applications. Using parallel arrays, on-currents of over 500 μA at a source-drain voltage of 0.5 V can be achieved. The transconductance is thus increased significantly while maintaining the transfer characteristics of single nanowire devices. By incorporating several hundred nanowires into the parallel array, the yield of functioning transistors is dramatically increased and deviceto-device variability is reduced compared to single devices. This new nanowirebased platform provides sufficient current output to be employed as a transducer for biosensors or a driving stage for organic light-emitting diodes (LEDs), while the bottom-up nature of the fabrication procedure means it can provide building blocks for novel printable electronic devices.      

Conversion of a Bi nanowire array to an array of Bi-Bi2O3 core-shell nanowires and Bi2O3 nanotubes

A template-based heat-treatment method has been developed to convert metal nanowire arrays into arrays of metal-metal oxide core-shell nanowires and single-crystalline metal oxide nanotubes. This process is demonstrated by kinetically controlling the conversion of single-crystalline Bi nanowires to Bi-Bi(2)O(3) core-shell nanowires via a multistep, slow oxidation method, and then controlling their further conversion to a single-crystalline Bi(2)O(3) nanotube array via fast oxidation. This process can conveniently be extended to fabricate a free-standing, easily oxidized metal-metal oxide nanowire and metal oxide nanotube array, which may have future applications in nanoscale optics, electronics, and magnetics.     

Bi2O3薄膜的制备及其电阻开关特性的研究

电阻式存储器由于具有众多的优点有望成为最有前景的下一代高速非挥发性存储器的选择之一.实验利用射频磁控溅射法在重掺硅上沉积了Bi2O3薄膜,并对该薄膜的结晶状态和Au/Bi2O3/n+Si/Al结构的电阻开关特性进行了研究.XRD分析结果表明,射频磁控溅射法沉积所得的Bi2O3薄膜结晶性能好,(201)取向明显.I-V曲线测试结果表明,Au/Bi2O3/n+Si/Al结构具有单极性电阻开关特性.通过对不同厚度Bi2O3薄膜的Au/Bi2O3/n+Si/Al结构I-V特性比较发现,随着薄膜厚度的增加,电阻开关的Forming、Set和Reset阈值电压均随之增加.对于Bi2O3薄膜厚度为31.2 nm的Au/Bi2O3/n+Si/Al结构,其Forming、Set和Reset阈值电压均低于4 V,符合存储器低电压工作的要求.     

Fully transparent thin-film transistor devices based on SnO2 nanowires

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.     

From InSb nanowires to nanocubes: looking for the sweet spot

High aspect ratios are highly desired to fully exploit the one-dimensional properties of indium antimonide nanowires. Here we systematically investigate the growth mechanisms and find parameters leading to long and thin nanowires. Variation of the V/III ratio and the nanowire density are found to have the same influence on the "local" growth conditions and can control the InSb shape from thin nanowires to nanocubes. We propose that the V/III ratio controls the droplet composition and the radial growth rate and these parameters determine the nanowire shape. A sweet spot is found for nanowire interdistances around 500 nm leading to aspect ratios up to 35. High electron mobilities up to 3.5 × 10(4) cm(2) V(-1) s(-1) enable the realization of complex spintronic and topological devices.     

The effect of Ga content on In₂xGa₂-₂xO₃ nanowire transistor characteristics

We have investigated the change in structural and electrical properties of In(2x)Ga(2-2x)O(3) nanowires (x = 1, 0.69 and 0.32) grown with varied indium (In) and gallium (Ga) contents. The as-grown In(2x)Ga(2-2x)O(3) nanowires kept the cubic crystal structure of In(2)O(3) intact even when the atomic percentages of Ga were increased to 31% (x = 0.69) and 68% (x = 0.32) in comparison to the total amount of In and Ga. However, as Ga added to In(2)O(3) structure was substituted with In, the lattice constant decreased and, consequently, the main peaks observed in x-ray diffraction in the direction of (222), (400) and (440) shifted by around ～0.08°. The average threshold voltage values for the In(2x)Ga(2-2x)O(3) nanowire transistors were -9.9 V (x = 1), -6.6 V (x = 0.67) and -5.6 V (x = 0.32), exhibiting a more positive shift and the sub-threshold slope increased to 0.53 V /dec (x = 1), 0.33 V /dec (x = 0.67) and 0.27 V /dec (x = 0.32), showing an improved switching characteristic with increasing Ga.     

Precise in situ tuning of the critical current of a superconducting nanowire using high bias voltage pulses

We present a method for in situ tuning of the critical current (or switching current) and critical temperature of a superconducting MoGe nanowire using high bias voltage pulses. Our main finding is that as the pulse voltage is increased, the nanowire demonstrates a reduction, a minimum and then an enhancement of the switching current and critical temperature. Using controlled pulsing, the switching current of a superconducting nanowire can be set exactly to a desired value. These results correlate with in situ transmission electron microscope imaging where an initially amorphous nanowire transforms into a single crystal nanowire by high bias voltage pulses. We compare our transport measurements to a thermally activated model of Little's phase slips in nanowires.     

Characterization of luminescence properties of V2O5-capped ZnSe nanowires

ZnSe-core/V2O5-shell nanowires were synthesized by the thermal evaporation of ZnSe powders on gold-coated Si (100) substrates followed by the sputter depositon of V2O5. Scanning electron microscopic images showed that the core-shell nanowires were a few tens to a few hundreds of nanometers in diameter and a few hundreds of micrometers in length. Transmission electron microscopy and X-ray diffraction analyses revealed that the core and shell of the core-shell nanowires were single crystal wurtzite-structured ZnSe and amorphous V2O5, respectively. Photoluminescence measurement showed that the core-shell nanowires as-synthesized or annealed in an oxidative atmosphere had a green emission band centered at around 520 nm whereas the as-synthesized ZnSe nanowires and the ZnSe-core/V2O5-shell nanowires annealed in a reducing atmosphere had a yellow emission band centered at around 590 nm. Our results also showed that V2O5 capping with an optimal thickness and subsequent annealing in a reducing atmosphere could significantly enhance the emission intensity of the ZnSe nanowires. In addition, the origins of the enhancement in intensity and the blue shift of the major emission by V2O5 capping are discussed.     

Nonvolatile Memory Elements Based on Organic Materials

Many organic electronic devices exhibit switching behavior, and have therefore been proposed as the basis for a nonvolatile memory (NVM) technology. This Review summarizes the materials that have been used in switching devices, and describes the variety of device behavior observed in their charge–voltage (capacitive) or current–voltage (resistive) response. A critical summary of the proposed charge‐transport mechanisms for resistive switching is given, focusing particularly on the role of filamentary conduction and of deliberately introduced or accidental nanoparticles. The reported device parameters (on–off ratio, on‐state current, switching time, retention time, cycling endurance, and rectification) are compared with those that would be necessary for a viable memory technology.     

Electrical breakdown and nanogap formation of indium oxide core/shell heterostructure nanowires

We report the electrical breakdown behavior and subsequent nanogap formation of In(2)O(3)/InO(x) core/shell heterostructure nanowires with substrate-supported and suspended structures. The radial heterostructure nanowires, composed of crystalline In(2)O(3) cores and amorphous In-rich shells, are grown by chemical vapor deposition. As the nanowires broke down, they exhibited two distinct current drops in the current-voltage characteristics. The tips of the broken nanowires were found to have a cone or a volcano shape depending on the width of the nanowire. The shape, the size, and the position of the nanogap depend strongly on the device structure and the nanowire dimensions. The substrate-supported and the suspended devices exhibit distinct breakdown behavior which can be explained by the diffusive thermal transport model. The breakdown temperature of the nanowire is estimated to be about 450?K, close to the melting temperature of indium. We demonstrated the usefulness of this technique by successful fabrication of working pentacene field-effect transistors.     

Quantum confinement induced performance enhancement in sub-5-nm lithographic Si nanowire transistors

We demonstrate lithographically fabricated Si nanowire field effect transistors (FETs) with long Si nanowires of tiny cross sectional size (～3-5 nm) exhibiting high performance without employing complementarily doped junctions or high channel doping. These nanowire FETs show high peak hole mobility (as high as over 1200 cm(2)/(V s)), current density, and drive current as well as low drain leakage current and high on/off ratio. Comparison of nanowire FETs with nanobelt FETs shows enhanced performance is a result of significant quantum confinement in these 3-5 nm wires. This study suggests simple (no additional doping) FETs using tiny top-down nanowires can deliver high performance for potential impact on both CMOS scaling and emerging applications such as biosensing.     

Fabrication and device characterization of omega-shaped-gate ZnO nanowire field-effect transistors

Omega-shaped-gate (OSG) nanowire-based field effect transistors (FETs) have attracted a great deal of attention recently, because theoretical simulations predicted that they should have a higher device performance than nanowire-based FETs with other gate geometries. OSG FETs with channels composed of ZnO nanowires were successfully fabricated in this study using photolithographic processes. In the OSG FETs fabricated on oxidized Si substrates, the channels composed of ZnO nanowires with diameters of about 110 nm are coated with Al(2)O(3) using atomic layer deposition, which surrounds the channels and acts as a gate dielectric. About 80% of the surfaces of the nanowires coated with Al(2)O(3) are covered with the gate metal to form OSG FETs. A representative OSG FET fabricated in this study exhibits a mobility of 30.2 cm(2)/ (V s), a peak transconductance of 0.4 muS (V(g) = -2.2 V), and an I(on)/I(off) ratio of 10(7). To the best of our knowledge, the value of the I(on)/I(off) ratio obtained from this OSG FET is higher than that of any of the previously reported nanowire-based FETs. Its mobility, peak transconductance, and I(on)/I(off) ratio are remarkably enhanced by 3.5, 32, and 10(6) times, respectively, compared with a back-gate FET with the same ZnO nanowire channel as utilized in the OSG FET.     

Controlled growth of ternary alloy nanowires using metalorganic chemical vapor deposition

We report the growth and characterization of ternary AlxGa1- xAs nanowires by metalorganic chemical vapor deposition as a function of temperature and V/III ratio. Transmission electron microscopy and energy dispersive X-ray spectroscopy show that, at high temperatures and high V/III ratios, the nanowires form a core-shell structure with higher Al composition in the nanowire core than in the shell. We develop a growth model that takes into account diffusion of reactants and decomposition rates at the nanowire catalyst and stem to describe the compositional difference and the shell growth rate. Utilizing this model, we have successfully grown compositionally uniform Al0.16Ga0.84As nanowires. The ability to rationally tune the composition of ternary alloy nanowires broadens the application range of nanowires by enabling more complex nanowire heterostructures.     

Self-organized Ce(1-x)Gd(x)O(2-y) nanowire networks with very fast coarsening driven by attractive elastic interactions

Assembling arrays of ordered nanowires is a key objective for many of their potential applications. However, a lack of understanding and control of the nanowires' growth mechanisms limits their thorough development. In this work, an appealing new path towards self-organized epitaxial nanowire networks produced by high-throughput solution methods is reported. Two requisites are identified to generate the nanowires: a thermodynamic driving force for an unrestricted elongated equilibrium island shape, and a very fast effective coarsening rate. These requirements are met in anisotropically strained Ce(1-x)Gd(x)O(2-y) nanowires with the (011) orientation grown on the (001) surface of LaAlO(3) substrates. Nanowires with aspect ratios above ≈100 oriented along two mutually orthogonal axes are obtained leading to labyrinthine networks. A very fast effective nanowire growth rate (≈60 nm min(-1)) for ex-situ thermally annealed nanostructures derives from simultaneous kinetic processes occurring in a branched network. Ostwald ripening and anisotropic dynamic coalescence, both promoted by strain-driven attractive nanowire interaction, and rapid recrystallization, enabled by fast atomic diffusion associated with a high concentration of oxygen vacancies, contribute to such an effective growth rate. This bottom-up approach to self-organized nanowire growth has a wide potential for many materials and functionalities.     

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.