基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

基于湿法表面活化处理的InP/SOI晶片键合技术

为了实现集成硅基光源,研究了基于湿法表面处理的InP/SOI直接键合技术。采用稀释的HF溶液对InP晶片进行表面活化处理,同时采用Piranha溶液对SOI晶片进行表面活化处理,实现了二者的低温直接键合。分别采用刀片嵌入法和划痕测试仪对样品的键合强度进行了定性及定量分析。同时,采用超声波扫描显微镜及扫描电子显微镜对键合界面的缺陷信息及键合截面的微观特性进行了评估。分析结果表明:提出的键合工艺可以获得较好的键合效果。     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

New layer transfers obtained by the SmartCut process

The SmartCut process was first developed to obtain silicon-on-insulator (SOI) materials. Now an industrial process, the main Unibond SOI-structure trends are reported in this paper. Many material combinations can be achieved by this process, because it appears to enable the generic development of new structures. Several of the new structures combining different materials and different bonding layers are described. These include SiGe and strained-Si films onto an oxidized Si wafer, silicon-on-insulating multilayer (SOIM) structures, and InP or 4H-SiC film transfers onto low-cost substrates via metallic or even refractory conductive-film bonding layers. More recently, an original bonding process based on mark patterning, wafer bonding, and layer transfer has been proposed to obtain structures in which the relative crystalline-axis orientations of both the film and the substrate can be controlled accurately. In this case, a SmartCut process that includes a mark-patterning step appears well suited for precise control of axis orientations. A procedure is described to obtain an ultra-thin Si film bonded onto a Si wafer. An example of a pure screw-dislocation network achieved by the mark patterning, bonding, and layer-transfer process is reported in this paper. The results have important implications for nanostructure development.     

Physics of direct bonding: Applications to 3D heterogeneous or monolithic integration

Direct wafer bonding and thinning technologies are now extensively used in combination to produce SOI wafers (silicon-on-insulators) or innovative engineered substrates. Emerging demands of new functionalities at the material or device level for 3D integration have allowed increasing the level of maturity of these technologies. This paper will review the physics of wafer direct bonding and its implementation for vertical integration devices of processed strata with vertical interconnects.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Grounded body SOI(GBSOI) nMOSFET by wafer bonding

We have fabricated a grounded body silicon-on-insulator (GBSOI) nMOSFET by wafer bonding and etch back technology. The GBSOI has all the inherent advantages of SOI such as speed and radiation hardness, while such problems as the low breakdown voltage and kink effect are completely solved due to the p⁺ polysilicon grounded body. It also has high packing density because several SOI bodies and the ground line are connected via the p⁺ polysilicon layer buried under the channel region     

晶圆键合技术在LED应用中的研究进展

简要介绍了晶圆键合技术在发光二极管(LED)应用中的研究背景,分别论述了常用的黏合剂键合技术、金属键合技术和直接键合技术在高亮度垂直LED制备中的研究现状,包括它们的材料组成和作用、工艺步骤和参数以及优缺点.其中,黏合剂键合是一种低温键合技术,且易于应用、成本低、引入应力小,但可靠性较差;金属键合技术能提供高热导、高电导的稳定键合界面,与后续工艺兼容性好,但键合温度高,引入应力大,易造成晶圆损伤;表面活化直接键合技术能实现室温键合,降低由于不同材料间热失配带来的负面影响,但键合良率有待提高.     

Transfer of semiconductor and oxide films by wafer bonding and layer cutting

Material integration by wafer bonding and layer transfer is one of the main approaches to increase functionality of semiconductor devices and to enhance integrated circuits (IC) performance. Even though most mismatches such as different lattice constants betweeen bonding materials present no obstacle for wafer direct bonding, thermal stresses caused by thermal mismatches must be minimized by low temperature bonding to avoid debonding, sliding or cracking. In order to achieve a strong bond at low temperatures, two approaches may be adopted: 1) Bonding at room temperature by hydrogen bonding of OH, NH, or FH terminated surfaces followed by polymerization to form covalent bonds. Within this approach the key is to remove the by-products of the reaction at the bonding interface. 2) Direct formation of a covalent bond between clean surfaces without adsorbents in ultra high vacuum conditions. Low temperature bonding allows bonding processed wafers for technology integration. Layer transfer requires uniform thinning of one wafer of a bonded pair. The most promising technology involves a buried embrittled region by hydrogen implantation. A layer with a thickness corresponding to the hydrogen implantation depth is then transferred onto a bonded desired substrate by either splitting due to internal gas pressure or by forced peeling as long as the bonding energy is higher than the fracture energy in the embrittled region at the layer transfer temperature. This approach is quite generic in nature and may be applied to almost all materials. We have found that B+H co-implantation and/or H implantation at high temperatures can significantly lower the splitting temperature. However, the wafer temperature during H implantation has to be within a temperature window that is specific for each material. The experimentally determined temperature windows for some semiconductors and single crystalline oxides will be given.     

Silicon-on-insulator Structure Fabricated by Epitaxial Layer Transfer

Epitaxial monocrystalline silicon film was grown on the porous silicon using ultra-high vacuum electron beam evaporation. Silicon-on-insulator(SOI) materials were successfully produced by bonding and etching the back of porous silicon. The quality of the SOI samples was investigated by using the cross-sectional transmission electron microscopy (XTEM), spreading resistance profile (SRP), atomic force microscopy (AFM) and four-crystal X-ray diffraction (FCXRD). Experimental results show the SOI sample has good properties. Besides, the factors resulting in lattice strain of this SOI structure and the methods to reduce it are given.     

Evaluation of the bonded silicon on insulator (SOI) wafer and thecharacteristics of PIN photodiodes on the bonded SOI wafer

Electrical properties of the bonded silicon on insulator (SOI) wafer and characteristics of PIN photodiodes fabricated on the SOI layer were evaluated. A trap with deep energy level (about Ec-Et=0.55 eV) was observed in the SOI layer with 100 μm- and 30 μm-thickness using the deep level transient spectroscopy (DLTS) method. No trap was detected in the SOI layer with 10 μm-thickness. This deep trap was not observed before the wafer bonding process and thus the trap is generated during the wafer bonding process. From primary mode lifetime (τ₁) measurements, it is considered that the trap will works as the generation center or the recombination center. For PIN photodiodes on the SOI layer in which the trap was detected, the increases of dark current were observed. Spectral responses of photodiodes on the SOI layer were almost the same as that on the normal FZ-Si wafer. We fabricated PIN photodiodes with good spectral response     

Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies

Schemes and key technologies of wafer-level three-dimensional integrated circuits (3D IC) are reviewed and introduced in this paper. Direction of wafer stacking, methods of wafer bonding, fabrication of through-silicon via (TSV), and classification of wafer type are options for 3D IC schemes. Key technologies, such as alignment, Cu bonding, and TSV fabrication, are described as well. Better performance, lower cost, and more functionality of future electronic products become feasible with 3D IC concept application.     

SOI Process Using Chemical Treatment and Bonding of Si Wafers

An SOI process including wafer bonding and splitting is developed and evaluated by experiment. Trial SOI wafers are fabricated and characterized. It is concluded that such wafers might serve as a starting point for making radiation-hardened, thermally stable ICs and special-purpose sensors and MEMS.     

半导体硅片键合:MEMS制造工序中的成熟技术(英文)

新型MEMS应用领域的发展为现有的制造技术带来了很大的挑战,并促使了满足新加工要求的制造能力的发展。根据目前MEMS制造中普遍采用的不同的晶圆键合方法及其主要工艺参数要求,开发了一种新型的晶圆键合技术。     

Bonding parameters of blanket copper wafer bonding

A reliable copper wafer bonding process condition, which provides strong bonding at low bonding temperature with a short bonding duration and does not affect the device structure, is desirable for future three-dimensional (3-D) integration applications. In this review paper, the effects of different process parameters on the quality of blanket copper wafer bonding are reviewed and summarized. An overall view of copper wafer bonding for different bonding parameters, including pressure, temperature, duration, clean techniques, and anneal option, can be established. To achieve excellent copper wafer bonding results, 400°C bonding for 30 min. followed by 30 min. nitrogen anneal or 350°C bonding for 30 min. followed by 60 min. anneal bonding is necessary. In addition, by meeting the process requirements of future integrated circuit (IC) processes, the best bonding condition for 3-D integration can be determined.     

Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes

This paper investigates and reviews the effects of wafer bow in three- dimensional (3D) integration bonding schemes, including copper wafer bonding and oxide fusion wafer bonding with silicon on insulator (SOI)-based layer transfer technology. Wafer bow criteria for good bonding quality and fabrication techniques to minimize wafer bow are introduced for 3D integration technology and applications.     

Fabrication and Characterization of 150-mm Silicon-on-Polycrystalline Silicon Carbide Substrates

Silicon-on-insulator (SOI) substrates can reduce radiofrequency (RF) substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps heat generated by devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of polycrystalline silicon and polycrystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable BOX and the silicon substrate. Substrates of 150 mm were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low-resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared with each other. Results showed that the Si-on-poly-SiC wafer had 2.5 times lower thermal resistance and exhibited equal or better electrical performance compared with the SOI reference wafer.     

基于硼酸溶液处理的GaAs/InP低温晶片键合技术

提出了一种基于硼酸溶液的GaAs/InP低温晶片键合技术,实现了GaAs/InP基材料间简单、无毒性的高质量、低温(290℃)晶片键合。GaAs/InP键合晶片解理截面的扫描电子显微镜(SEM)图显示,键合界面整齐,没有裂缝和气泡。通过键合过程,InP上的In0.53Ga0.47As/InP多量子阱结构转移到了GaAs基底上。X射线衍射及荧光谱显示,键合后的多量子阱晶体质量未变。二次离子质谱(SIMS)和Raman光谱图显示,GaAs/InP键合晶片的中间层厚度约为17 nm,界面处B元素有较高的浓度,键合晶片的中间层很薄,因此可以得到较好的电学、光学特性。     

晶片键合质量的红外检测系统设计

基于晶片的红外透射原理,设计并搭建了晶片直接键合质量红外检测装置,并利用图像处理技术开发了相应的软件模块,可以快速获取键合界面的特性参数,如空洞分布、大小及键合率等,从而实现晶片直接键合质量的快速评估.同时,将该红外检测装置与硅片键合装置结合一体,可以实时监测硅片直接键合工艺.通过分析不同工艺条件下所获得的键合片质量,包括键合率、缺陷分布以及键合强度等参数的比较,可以有助于理解晶片键合的机理,实现键合工艺的优化.