可编程器件的选择性双模冗余加固方法

针对现有FPGA加固方法开销过大的问题,提出一种利用逻辑门对故障的屏蔽效应进行选择性加固的双模冗余方法.首先建立待加固电路的查找表结构模型,根据故障的传播概率按电路结构依次计算每个查找表的故障敏感度;然后将故障敏感度高的查找表进行双模冗余,并根据要屏蔽的故障类型在冗余后的查找表输出端添加"与","或"逻辑进行表决;最后对加固后的电路进行故障注入,验证加固效果.对MCNC测试集电路的实验结果表明,与现有方法相比,在同等开销下,文中方法对故障的屏蔽效果更显著;全冗余时,该方法可将故障平均减少84.3%,对于apex2,spla等大电路则能减少超过97%.     

固定型故障完全可测异步控制电路设计

本文基于直接映射技术和异步控制电路的故障自检测特性,提出了一种固定型故障完全可测的异步控制电路设计方法,并在此基础上对异步控制电路单固定型故障的测试策略进行了较为详细的阐述。结果表明本方法切实有效且额外的面积开销小。     

冗余式高压直流无刷电机控制系统设计

在冗余式高压直流无刷电机基本结构的基础上,研究了冗余式高压直流无刷电机的控制策略,设计了一套基于DSP的冗余式高压直流无刷电机控制系统;该系统主要分为控制电路、隔离电路、驱动电路、主功率电路、故障检测与保护电路和系统供电电源模块等;系统采用专用电机控制集成芯片TMS320F2812为控制核心,实现了总线控制、电机余度工作模式的切换、正/反转运行、故障检测与保护等功能;系统采用转速闭环控制策略,实验结果表明系统动态响应快,稳速精度高,并在两个余度同时工作时实现了电流的均衡.     

常用数字集成电路的在系统自动检测

介绍了电子设备工作中常用数字集成电路的故障自检。根据各类器件的逻辑特点及其在应用电路中的作用,利用数字电路的冗余功能,分别研究了其在系统中工作的同时进行故障自检的方法。该方法故障覆盖率不高,但简单实用,易于实现。文中还研究了同类器件在电子系统中的联动检测方法,进一步简化自检电路,并通过计算机进行了仿真和部分实验验证     

基于能量熵对SVM的电路故障诊断

研究电路故障诊断问题,提高诊断效率.由于电路集成度提高,电路信号与故障相关,针对传统故障诊断因采用线性诊断方法与提取的电路特征信息不全面,导致诊断定位精度不高,为有效提高电路故障诊断的速度与精度,提出了一种根据小波包能量熵的支持向量机电路故障诊断方法(EE-SVM).首先利用小波包对电路故障信号进行3层的小波包分解,并提取小波包能最熵,构建输入特征向量.对于支持向量机进行非线性特征向量汰选,去除冗余特征,以保留特征向量构建智能化诊断模型.进行实例仿真,结果显示,方法在所有参比模型中精度最高,能高效地对电路故障进行检测与定位.     

一种基于动态可测性测度的快速识别逻辑冗余故障的方法—DRFM

在测试生成之前,借助可测性分析方法,以线性时空开销识别数字电路的冗余故障是个至今尚未解决的问题.本文在文献[8,9]的四值动态代价分析的基础上,首次采用动态相关信号模型,提出了动态约束四值测度方法DRFM.DRFM能精确描述实用电路中常见的冗余故障,它识别一个冗余故障所需的时间为电路门数的线性增长函数.     

一种新的基于固定型故障的通路时延故障可测试性分类方法

在数字电路的时延测试、时序分析和时序优化中都会用到不可测通路时延故障的识别。本文通过简单的变换将原电路展开，然后对原电路里的伪时序通路(false timing paths)和展开后的电路里的冗余固定型故障建立一种很强的关系。已经证明过通路时延故障测试是时延测试里最精确的形式。     

多输出组合电路的自检测

本文叙述了对于有扇出的多输出组合电路进行误差检测的一般方法,详细地讨论了这种方法的误差检测特性,任何组合电路的输出误差都可预测,因而整个电路可设计成对于任何单固定故障为完全自检的。     

基于主成分分析和奇偶向量的动态检测方法

导航系统中冗余IMU传统故障检测方法由于数学模型过于复杂,计算量大,存在较大延时,难以实现实时故障检测,而主成分分析法仅仅应用于静态情况下的故障检测与隔离,针对主成分分析法无法在动态情况下对冗余IMU进行故障检测的缺点,提出了一种基于奇偶空间法改进主成分分析的故障检测算法,该方法利用奇偶向量隔离车辆的动态变量,以消除动态变量对故障检测的影响,再用PCA方法检测数据以实现对车辆传感器信息的实时检测,通过将原始数据集转置到特征平面来形成图案,实现了IMU传感器正常与故障模式的准确分离,提高了冗余IMU故障检测的结果精确性和可靠性。实验结果表明,该方法能够较好检测动态状态下冗余IMU的故障,提高了主成分分析的故障检测性能,可有效消除导航系统运动的负面影响。     

双机热备容错逻辑控制电路设计与仿真

针对传统数字电路系统冗余设计复杂、切换时间长、实现电路体积大等问题,提出一种双机热备容错逻辑控制电路的设计方案.使用VHDL语言设计、一片CPLD芯片实现工作微处理器系统的故障检测与主、备微处理器系统的实时切换等时序控制功能.时序仿真结果表明,该电路判断故障成功率高,切换时间短,可以满足强实时性嵌入式系统的双机热备冗余设计.在高可靠性的微机保护系统等应用场合,该硬件冗余设计方案具有工程设计指导意义.     

ANALYZING MULTIPLE FAULTS IN SYNCHRONOUS SEQUENTIAL CIRCUITS BY BOOLEAN DIFFERENCE TECHNIQUES

The Boolean difference is a mathematical concept that has proved its usefulness in the study of single and multiple “stuck-at” faults in combinational circuits. Goldstein has extended his tool of analysis to cover the multiple stuck-at faults Asynchronous sequential circuits. In this paper, modifications to Goldstein's paper are presented, together with a new method for deriving the required shortest test sequence to detect a specified multiple fault.     

A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults

A new classification of path-delay fault testability in a combinational circuit is presented in terms of testability of stuck-at faults in an equivalent circuit. Earlier results describing correlation of path-delay and stuck-at faults are either incomplete, or use a complex model of equivalent circuit based on timing parameters. It is shown here that a path-delay fault (rising or falling) is testable if and only if certain single or multiple stuck-at fault in the equivalent circuit is testable. Thus, all aspects of path-delay faults related to testability under various classification schemes can be interpreted using the stuck-at fault model alone. The results unify most of the existing concepts and provide a better understanding of path-delay faults in logic circuits.     

IDDT: Fundamentals and Test Generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

IDDQ test and diagnosis of CMOS circuits

Designers must target realistic faults if they desire high-quality test and diagnosis of CMOS circuits. The authors propose a strategy for generating high-quality I_DDQ test patterns for bridging faults. They use a standard ATPG tool for stuck-at faults that adapts to target bridging faults via I_DDQ testing. The authors discuss I_DDQ test set diagnosis capability and specifically generated vectors that can improve diagnosability, and provide test and diagnosis results for benchmark circuits     

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.     

系统芯片IP核透明路径构建中的可测性分析

系统芯片的设计方法为测试技术带来新挑战。知识产权模块（IP核）测试访问机制成为测试复用的关键。构建IP核透明路径会对电路的故障覆盖率产生影响。基于门级透明路径的构建方法，通过分析插入电路的控制门和多路器的激活和传播条件，对路径构建对于IP核单固定型故障覆盖率的影响进行分析，给出可测性条件和故障覆盖率的计算公式，无需故障仿真即可估计构造透明路径后电路的故障覆盖率。通过故障仿真实验，证明该故障覆盖率的分析和计算方法是有效的。     

基于混沌搜索的数字电路多故障测试生成

针对数字电路中多故障测试生成较难的问题,本文提出了基于混沌搜索的数字电路多故障测试生成算法。该算法先把多故障转换成为单故障,再用神经网络的方法对单故障电路构造故障的约束网络,最后用混沌搜索方法求解故障约束网络能量函数的最小值点获得原电路中多故障的测试矢量。在一些国际标准电路上的实验结果表明了本算法的可行性。     

Near-minimal test sets for the detection of single gate faults

A new algorithm is presented for the detection of single gate faults in combinational networks. A gate fault is any unknown transformation of the Boolean function realized by a particular gate or single-output subnetwork. Detection of such faults is accomplished by verifying the truth table of the correct gate function.The concept of real transform of a Boolean function is utilized to obtain in each iteration an optimal test, namely, a test that performs as much of the fault detection task as possible. The resulting test set is near-minimal and complete.The algorithm can handle multi-output networks, integrated network components and mixed (gate, stuck-at) fault models.