CAD tools for the synthesis and layout of SC filters and networks

This paper describes two programs for the synthesis and layout generation of SC filters and networks. The first part of the paper describes a technology-independent synthesis and optimization program for SC filters. The program allows for the exact synthesis of cascaded SC biquad and SC ladder filters. Two performance measures related to sensitivity and noise are employed to estimate the performance of the synthesized circuits and to select optimum realizations. The same measures are used in a novel capacitance assignment procedure. The second part of the paper describes a flexible SC layout generator, which can be adapted to various design rules and floorplans by means of a technology file. Area efficient layout is generated by placing individual circuit elements rather than building blocks. Crosstalk between conductors is minimized by a router that distinguishes between different kinds of nodes.1. The scaling of the biquad circuit is dependent on the position of the biquad in the cascade.2. This may not seem to be overly important, since high-pass-type filters do not occur that often in practical applications. If one considers, however, that SCSYN is to be used as a general filter synthesis program, thenevery filter must be automatically realizable. In such an environment, a CAD program that can design all but one type of filter is either quite useless or very limited indeed.3. Note that an SC filter, in contrast to a digital filter, may contain delay-free loops.     

Microelectronic switched capacitor filters

An explanation of what switched-capacitor (SC) filters are and how they work is given. Attention is focused on low-sensitivity SC filters, which can be developed from a general passive ladder where the branches are arbitrary impedances. The equations that describe the filter components are reviewed, and the characteristics of these low-sensitivity filters are outlined. Applications of the filters in telecommunications are discussed     

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

Losslessness and stability of LDI ladders and filters

The stability of digital ladder filters close in form, via the lossless discrete integrator (LDI) transformation, to doubly terminatedLC Cauer ladder low-pass filters is studied. The LDI transformation does not necessarily map stable analogue into stable digital filters. Necessary and sufficient conditions for these digital filter to be lossless and for a corresponding doubly terminated filter to be stable are given. LDIs are often used in the design of switched capacitor (SC) filters. For this case we provide a threshold sampling rate above which the SC LDI filter retains the stability of the analogue filter. In spite of the stability problem with the LDI mapping, it has been observed that when applied to simulate analogue filters the resulting filter is stable. It can now be argued that, in these cases, other factors in the determination of the sampling rate leads typically to a choice that is also sufficiently above the threshold rate for stability. The theory described is also useful to derive more general digital filters and to perform the design of stable LDI filters exclusively in the Z-plane without reference to analogue prototypes.This work was partly supported by the U.S.-Israel Binational Science Foundation under Grant No. 88-425.     

Switched-capacitor filters

A novel technique for building active filters using switched-capacitor (SC) circuits is proposed. Principles of operation, methods of control, analysis, and design of a typical SC filter are presented. To assess its effectiveness, the technique is used to control input current harmonics in a phase-controlled converter. It is shown that a wide range of harmonics can be controlled using a single filter     

基于信号流图的开关电流滤波器设计

开关电流（SI）是有望取代开关电容（SC）的一种新型的取样数据技术，鉴于SC技术发展的成熟性及其与SI技术的紧密联系，即SC和SI滤波电路具有互易性，可采用信号流图转置的方法，将SC综合法直接用于SI滤波器设计，而无须提出新的设计方法。本文以二阶巴特沃思开关电容带通滤皮器为例给出了该方法的具体应用。     

An integrated CMOS switched-capacitor bandpass filter based on N-path and frequency-sampling principles

A new combined switched-capacitor (SC) frequency-sampling N-path filter is presented, which allows the implementation of very narrow bandpass filters. The included frequency-sampling (FS) filter suppresses undesirable passbands of the SC N-path filter. The center frequency f/SUB m/ of the bandpass filter is identical to the circuit clock frequency f/SUB c/. Experimental results are presented for a CMOS SC frequency-sampling four-path filter with second-order filter cells, a center frequency of 1 kHz, and -3-dB passband bandwidth of 11.5 Hz.     

A reduced capacitor spread algorithm for elliptic bandpass SC filters

A modification of a well-known algorithm for simulating elliptic LC ladder filters by switched-capacitor (SC) technique is presented, The filter terminations were realized without damped integrators. The modification was proven useful in reducing the capacitance spread and total capacitance in high-Q bandpass SC filters: improvements by factors of five and six were obtained in the design of sixth- and tenth-order bandpass filters, respectively. A chip, including four sixth-order bandpass filters in the audio range, was designed and found to function properly.     

A switched-capacitor preprocessor for speech recognition

A switched-capacitor (SC) preprocessing system (preprocessor) which extracts and emphasizes the local peaks of the spectrum in real time is proposed for speech recognition systems. Main components of the system are a specially designed bandpass filter bank, a low-pass decimation filter bank, two-dimensional local peak extraction (LPE) filters, and a LPE filter selection circuit. Furthermore, a SC cascaded integrator-comb filter design technique is proposed to realize the decimation low-pass filter and the LPE filter. Finally, the system is tested by using two speech recognition systems.     

Offset-compensated switched-capacitor leapfrog filters

Offset-compensated SC leapfrog filters can be realised as shown in the letter. The filters are parasitic-insensitive and the switches are controlled by a 3-phase clock. A 5th-order lowpass filter is given as an example.     

NEW STRUCTURE OF SC FILTERS WITH REDUCED GB EFFECT

In this paper, the problem how to reduce the GB effect in SC filters is discussed. A new generalbiquadratic SC structure in which the GB effect is reduced is developed. The structure is stray-insensitiveand has very low W_0 and Q sensitivities. Using the low-pass SC filter for an example, method of reducingthe GB effect has been shown in detail.     

Novel switched-capacitor pseudo-N-path filter

The letter presents novel fully stray-insensitive switched-capacitor (SC) pseudo-N-path filters based on the theory of wave-flow networks. N-path filters are well suited for the realisation of narrowband bandpass and bandreject filters. The two main drawbacks of N-path filters, i.e. unwanted mirror frequencies due to path mismatch, and clock feedthrough located in the passband, are overcome by applying the pseudo-N-path principle. The design procedure will be demonstrated using an example of a 6-path filter based on a 3rd-order highpass prototype filter.     

Integrated CMOS GSM baseband channel selecting filters realized using switched capacitor finite impulse response technique

A problem of the design and optimization of analog channel selecting filters, which are needed in wireless communication systems, is considered and evaluated in this paper on an example of the baseband GSM (global system for mobile telephony) channel filter. Two versions of this filter, both designed by the authors using switched-capacitor finite impulse response (SC FIR) technique, are presented and compared to each other as well as to other concurrent designs. In order to fully and plausibly compare the both filter versions (the newer and the elder one), the authors decided to design and fabricate both filters using the same technology, i.e., the technology of the elder filter version, which is the two metal, two poly CYE CMOS 0.8 μm process. The conclusions, which have been drawn, are, however, general and to a large extent technology independent.Although both presented filters are switched-capacitor (SC) finite impulse response (FIR) systems [Dąbrowski A, Cetnarowicz D, Długosz R, Pawłowski P. Design and optimisation of integrated CMOS FIR SC channel filter for a GSM Receiver, European Conference on Circuit Theory and Design, Helsinki, 28–31 August 2001. p I.265; Długosz R, Dąbrowski A, Pawłowski P. Design and measurement results of the GSM SC FIR channel filter realized in CMOS 0.8 μm technology. In: 9th international conference mixed design of integrated circuits and systems, 2002. p. 607–12] they essentially differ to each other as they are based on two quite different SC FIR delay line structures. In the first filter version Gillingham delay elements [Gillingham P. Stray-free switched-capacitor unit delay circuit. Electron lett 1984;20(7):308–10] are used, while in the second version even and odd delay elements [Dąbrowski A. Multirate and multiphase switched-capacitors circuits, London: Chapman & Hall; 1997; Dąbrowski A, Menzi U, Moschytz GS. Design of switched-capacitor FIR filters with application to a low-power MFSK receiver. IEE Proceedings-G 1992;139(4):450] are alternately connected to form the delay line. In this way an interesting comparison of these two SC delay line concepts has been possible.It should also be stressed that the frequency responses of both presented filters have been designed using the same technique, i.e., the Kaiser window of order N = 31. The upper frequency is in both cases equal to 500 kHz and the frequency of the controlling clock generator is equal to 1 MHz.The filter with Gillingham delay elements dissipates 30 mW with the 3 V supply voltage and occupies 2.2 mm². On the contrary, the even–odd SC FIR filter dissipates 18 mW only with the 3 V supply voltage and occupies 2.4 mm². Moreover, the newer filter version has the stopband attenuation greater by about 10 dB than the previous version.     

Noise-cancelling switched-capacitor (SC) filtering technique

A method of reducing the 1/f noise in SC filters is shown using an initialising technique. This technique also removes the input offset of the operational amplifier, and thus gives an offset-free SC building block. Experimental results for a first-order lowpass filter illustrating the above are presented.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

An optimum CMOS switched-capacitor antialiasing decimating filter

An optimum switched-capacitor (SC) decimating filter is capable of achieving a high input sampling frequency while the time period for the setting of the operational amplifiers can be maximized with respect to the lower output sampling frequency. Thus, for the same speed of the operational amplifiers, the oversampling ratio of the input signal in optimum SC decimating filters is much larger than in conventional SC filtering circuits, yielding a significant relaxation of the continuous-time prefiltering requirements. This is demonstrated by considering the design of a second-order SC antialiasing decimating filter with a threefold sampling rate reduction, which has been realized in a 1.8-μm CMOS double-poly technology. The experimental evaluation of prototype samples confirms the expected operation of the circuit     

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.     

A 3.6-MHz cutoff frequency CMOS elliptic low-pass switched-capacitor ladder filter for video communication

The high frequency (HF) behavior of the switched-capacitor (SC) LDI ladder filter is studied. This study shows that using low sampling frequency with respect to the cutoff frequency reduces the HF error due to the reduction in amplifier gain. Design techniques are also given for the HF SC filters, such as double-sampling scheme, a low sampling frequency with an exact synthesis algorithm, as well as a fast-settling folded-cascode amplifier. These techniques are applied to an experimental fifth-order elliptic SC filter fabricated in a 2-/spl mu/m CMOS technology. The experimental results show that a 3.6-MHz cutoff frequency is attained. All the capacitors are scaled down in order to reduce the setting time of the amplifiers. The active area of the filter is 0.9 mm/SUP 2/. The F/SUB sampling//F/SUB cutoff/ is only 5. The circuit operates from /spl plusmn/5 V and typically dissipates 80 mW when sampled at 18 MHz.     

Exact design of highpass switched-capacitor filters of the LDI type

The letter presents a technique by means of which stray-insensitive SC highpass ladder filters may be designed without the need for network synthesis. The starting point is a unit-element cascade (i.e. lowpass prototype from which the corresponding highpass filter is obtained by direct frequency transformation.     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.