RF HBT oscillators with low-phase noise and high-power performance utilizing a (/spl lambda//4/spl plusmn//spl delta/) open-stubs resonator

This paper presents a new type of transmission-line resonator and its application to RF (microwave and millimeter-wave) heterojunction bipolar transistor (HBT) oscillators. The resonator is a parallel combination of two open stubs having length of /spl lambda//4/spl plusmn//spl delta/(/spl delta//spl Lt//spl lambda/), where /spl lambda/ is a wavelength at a resonant frequency. The most important feature of this resonator is that the coupling coefficient (/spl beta//sub C/) can be controlled by changing /spl delta/ while maintaining unloaded Q-factor (Q/sub u/) constant. Choosing a small value of /spl delta/ allows us to reduce /spl beta//sub C/ or equivalently to increase loaded Q-factor (Q/sub L/). Since coupling elements such as capacitors or electromagnetic gaps are not needed, /spl beta//sub C/ and Q/sub L/ can be precisely controlled based on mature lithography technology. This feature of the resonator proves useful in reducing phase noise and also in enhancing output power of microwave oscillators. The proposed resonator is applied to 18-GHz and 38-GHz HBT oscillators, leading to the phase noise of -96-dBc/Hz at 100-kHz offset with 10.3-dBm output power (18-GHz oscillator) and -104-dBc/Hz at 1-MHz offset with 11.9 dBm (38-GHz oscillator). These performances are comparable to or better than state-of-the-art values for GaAs- or InP-based planar-circuit fundamental-frequency oscillators at the same frequency bands.     

Analysis of a Microwave Resonator-Feedback Oscillator (Correspondence)

The temperature stability of the oscillation frequency, (/spl Delta//spl omega/ / /spl omega/)/ /spl Delta/T, of an S-band feedback oscillator is derived in terms of the temperature stability of the stable resonator and that of the circuits external to the resonator. Conditions have been established for the optimum external circuit to achieve temperature stability of the oscillation frequency.     

A 300-/spl mu/W 1.9-GHz CMOS oscillator utilizing micromachined resonators

A low-power low-phase-noise 1.9-GHz RF oscillator is presented. The oscillator employs a single thin-film bulk acoustic wave resonator and was implemented in a standard 0.18-/spl mu/m CMOS process. This paper addresses design issues involved in codesigning micromachined resonators with CMOS circuitry to realize ultralow-power RF transceiver components. The oscillator achieves a phase-noise performance of -100 dBc/Hz at 10-kHz offset, -120 dBc/Hz at 100-kHz offset, and -140 dBc/Hz at 1-MHz offset. The startup time of the oscillator is less than 1 /spl mu/s. The oscillator core consumes 300 /spl mu/A from a 1-V supply.     

Measuring the /spl omega/ - /spl beta/ Diagram of Periodic Structures (Correspondence)

One of the most important properties of a periodic structure is the shape of the /spl omega/ - /spl beta/ diagram. A common technique for measuring the /spl omega/ - /spl beta/ diagram is to form a resonant section by placing shorting planes at positions of symmetry within the periodic structure and to observe the resonant frequencies of the resulting resonator. Discussed in this correspondence is a technique wherein the far end of the periodic structure is shorted and the positions of nulls of voltage on an input line are observed as frequency is varied. From these nulls it is possible to determine the frequencies where the electrical length of the loaded structure is a multiple of /spl pi/ radians. Basically, it is a procedure for graphically determining points on the /spl omega/ - /spl beta/ diagram.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

Modelling and Experiment of a Silicon Resonant Pressure Sensor

Modelling of a silicon resonator as a pressure sensor is presented. The resonator is electrothermally excited and the resonance frequency shift is detected by a piezoresistive thin film detector. Computer simulation using the commercial MEMS software tool IntelliSuite is compared with analytical model. Various design aspects, such as the pressure sensitivity, electrothermal heating of vibrating beam, influence of detection current and damping effect are investigated. Silicon resonator sensors have been fabricated and measured. The characteristics predicted by computer simulation has been confirmed by experimental results.     

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.     

Precise 90/spl deg/ quadrature current-controlled oscillator tunable between 50-130 MHz

A VLSI continuous time sinusoidal OTA-C quadrature oscillator fabricated in a standard double-poly 0.8 /spl mu/m CMOS process is presented. The oscillator is tunable in the frequency range from 50-130 MHz. The two phases produced by the oscillator show an extremely low phase difference error (less than 2/spl deg/ over the whole frequency range). A novel current mode amplitude control scheme is developed that allows for very small amplitudes. Experimental results are provided.     

1-GHz, 200/spl deg/C, SiC MESFET Clapp oscillator

A SiC Clapp oscillator fabricated on an alumina substrate with chip capacitors and spiral inductors is designed for high-temperature operation at 1GHz. The oscillator operated from 30/spl deg/C to 200/spl deg/C with an output power of 21.8dBm at 1GHz and 200/spl deg/C. The efficiency at 200/spl deg/ C is 15%. The frequency variation over the temperature range is less than 0.5%.     

Resonant Frequency of a TE//sub 01delta//spl deg/ Dielectric Resonator

The resonant frequency of a TE/sub 01delta//spl deg/ dielectric resonator was obtained by assuming a cylindrical surface containing the circumference of a dielectric resonator as a magnetic wall. In such a method, the error was less than 10 percent. In this short paper, the resonant frequency is obtained by a variational method, where the surface impedance is variated from a infinite value. The theoretical value of a resonant frequency has a good agreement with our experimental result with an error less than 1 percent.     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.     

A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery circuit

A 200-Mbps/spl sim/2-Gbps continuous-rate clock-and-data-recovery (CDR) circuit using half-rate clocking is presented. To detect the data with wide-range bit rates, a frequency tracing circuit (FTC) is used to aid the frequency acquisition. A wide-range and low gain voltage-controlled oscillator (VCO) is also presented by using analog and digital controlled mechanisms. A two-level bang-bang phase detector is utilized to improve the jitter performance and speed up the locking process. This CDR circuit has been realized in a 2P4M 0.35-/spl mu/m CMOS process. The experimental results show that this CDR circuit with the proposed FTC can receive 2/sup 31/-1 pseudorandom bit stream when the bit rate ranges from 200 Mbps to 2 Gbps without the harmonic-locking issue. All measured bit error rates are below 10/sup -12/. The measured root-mean-square and peak-to-peak jitters are 5.86 ps and 41.8 ps, respectively, at 2 Gbps.     

Linear analysis of the influence of FIR feedback filters on the response of the pulsed digital oscillator

The objective of this work is to extend the linear analysis of Pulsed Digital Oscillators to those topologies having a Finite Impulse Response (FIR) in the feedback loop of the circuit. It will be shown with two specific examples how the overall response of the oscillator can be adjusted to some point by changing the feedback filter, when the resonator presents heavy damping losses. Extensive discrete-time simulations and experimental results obtained with a MEMS cantilever with thermoelectric actuation and piezoresistive position sensing are presented. It will be experimentally shown that the performance of the oscillator is good even below the Nyquist limit.     

A 15-GHz broad-band /spl divide/2 frequency divider in 0.13-/spl mu/m CMOS for quadrature generation

This letter presents a 0.13-/spl mu/m CMOS frequency divider realized with an injection-locking ring oscillator. This topology can achieve a larger input frequency range and better phase accuracy with respect to injection-locking LC oscillators, because of the smoother slope of the loop gain phase-frequency plot. Post layout simulations show that the circuit is able to divide an input signal spanning from 7 to 19GHz, although the available tuning range of the signal source limited the experimental verification to the interval 11-15GHz, featuring a 31% locking range. The divider dissipates 3mA from a 1.2-V power supply.     

Frequency stability of Ti/sup 3+/-doped whispering gallery mode sapphire resonator oscillator at 34 K

The operation of a 12.7 GHz cryogenic oscillator based on a whispering gallery mode resonator doped with Ti/sup 3+/ ions is presented. The resonator operates at 34 K and exhibits a frequency stability order 2/spl times/10/sup -13/ for 8 s相似文献   

V-band harmonic injection-locked frequency divider using cross-coupled FETs

A V-band 1/2 frequency divider is developed using harmonic injection-locked oscillator. The cross-coupled field effect transistors (FETs) and low quality-factor microstrip resonator are employed as a wide-band oscillator to extend the locking bandwidth. The second harmonic of free-running oscillation signal is injected to the gates of cross-coupled FETs for high-sensitivity superharmonic injection locking. The fabricated microwave monolithic integrated circuit frequency divider using 0.15-/spl mu/m GaAs pHEMT process showed a maximum locking range of 7.4 GHz (from 65.1 to 72.5 GHz) under a low power dissipation of 100 mW. The maximum single-ended output power was as high as -3 dBm.     

Superconducting bandpass /spl Delta//spl Sigma/ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate

This paper presents a superconducting bandpass /spl Delta//spl Sigma/ modulator for direct analog-to-digital conversion of radio frequency signals in the gigahertz range. The design, based on a 2.23-GHz microstrip resonator and a single flux quantum comparator, exploits several advantages of superconducting electronics: the high quality factor of resonators, the fast switching speed of the Josephson junction, natural quantization of voltage pulses, and high circuit sensitivity. The modulator test chip includes an integrated acquisition memory for capturing output data at sampling rates up to 45 GHz. The small size (256 b) of the acquisition memory limits the frequency resolution of spectra based on standard fast Fourier transforms. Output spectra with enhanced resolution are obtained with a segmented correlation method. At a 42.6-GHz sampling rate, the measured SNR is 49 dB over a 20.8-MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2-GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6-MHz bandwidth. The modulator test chip contains 4065 Josephson junctions and dissipates 1.9 mW at T=4.2 K.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

A novel InGaP/InGaAs/GaAs double /spl delta/-doped pHEMT with camel-like gate structure

The author reports a novel InGaP/InGaAs/GaAs double delta-doped pseudomorphic high-electron mobility transistor (pHEMT) with n/sup +/-GaAs/p/sup +/-InGaP/n-InGaP camel-like gate structure grown by MOCVD. Due to the p-n depletion from the p/sup +/-InGaP gate to the channel region and the presence of /spl Delta/Ec at the InGaP/InGaAs heterostructure, the turn-on voltage of gate is larger than 1.7 V. For a 1/spl times/100-/spl mu/m/sup 2/ device, the experimental results show an extrinsic transconductance of 107 mS/mm and a saturation current density of 850 mA/mm. Significantly, an extremely broad gate voltage swing larger than 6 V with above 80% maximum g/sub m/ is obtained. Furthermore, the unit current cut-off frequency f/sub T/ and maximum oscillation frequency are up to 20 and 32 GHz, respectively. The excellent device performance provides a promise for linear and large signal amplifiers and high-frequency circuit applications.