Superconducting bandpass /spl Delta//spl Sigma/ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate

This paper presents a superconducting bandpass /spl Delta//spl Sigma/ modulator for direct analog-to-digital conversion of radio frequency signals in the gigahertz range. The design, based on a 2.23-GHz microstrip resonator and a single flux quantum comparator, exploits several advantages of superconducting electronics: the high quality factor of resonators, the fast switching speed of the Josephson junction, natural quantization of voltage pulses, and high circuit sensitivity. The modulator test chip includes an integrated acquisition memory for capturing output data at sampling rates up to 45 GHz. The small size (256 b) of the acquisition memory limits the frequency resolution of spectra based on standard fast Fourier transforms. Output spectra with enhanced resolution are obtained with a segmented correlation method. At a 42.6-GHz sampling rate, the measured SNR is 49 dB over a 20.8-MHz bandwidth, and a full-scale (FS) input is -17.4 dBm. At a 40.2-GHz sampling rate, the measured in-band noise is -57 dBFS over a 19.6-MHz bandwidth. The modulator test chip contains 4065 Josephson junctions and dissipates 1.9 mW at T=4.2 K.     

A 155-MHz clock recovery delay- and phase-locked loop

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth     

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally