A Fully Multiplexed First-Order Frequency-Planar Module for Fan, Beam, and Cone Plane-Wave Filters

A VLSI architecture for the on-chip realization of a first-order two-dimensional (2-D) or three-dimensional (3-D) infinte impulse response (IIR) fully multiplexed frequency-planar filter module (FMFPM) is proposed. Such filter modules may be used in 3-D video processing and 2-D/3-D plane-wave filtering using sensor arrays. The proposed FMFPM can potentially be used as a 2-D/3-D IIR building block circuit for the on-chip realization of second- (or higher) order frequency-planar filters, 3-D IIR beam filters, 2-D IIR fan filter banks and 3-D IIR cone filter banks.     

A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters

For high-speed plane-wave filtering applications, real-time 2-D spatio-temporal linear-array broadband beam filters are required, operating at temporal frame rates in excess of hundreds of megahertz. The corresponding application specific VLSI circuits must have low critical-path latencies. A novel high-speed systolic array architecture for a first-order 2-D broadband frequency-planar spatio-temporal beam filter is proposed for this purpose and employs a field-programmable gate array (FPGA) circuit where the critical path latency is minimized by timing optimization of inter- and intra-parallel processor pipelines, together with 3-D look-ahead techniques. The method facilitates single-chip VLSI circuit implementations operating at real-time frame rates of several hundred megahertz.      

Reducing the Multiplier-Complexity of Massively Parallel Polyphase 2D IIR Broadband Beam Filters

The superior broadband performance of 2D IIR frequency-planar beam filters, relative to conventional 2D FIR true-time-delay beamforming, has recently been reported using computational electromagnetics and real-time emulations on an antenna test range, resulting in significant improvements of bit-error-rates (BERs) in the presence of broadband interference. Further, massively parallel systolic VLSI circuit polyphase architectures have also been reported (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) for the case of the direct-form signal flow graph (SFG) architecture, operating at a maximum throughput of M-(antenna)-frames-per-clock-cycle (MFPCC). The superior broadband performance of 2D IIR frequency-planar beam filters is extended here from the direct-form signal flow graph (SFG) architecture (Madanayake et al. in Int. J. Circuit Theory Appl. 2010) to the novel differential-form SFG architecture in order to reduce overall complexity. The proposed method employs a differential-form polyphase 2D IIR frequency-planar beam SFG, and a corresponding circuit architecture, to implement the required input-output 2D space-time difference equation. The resultant digital hardware has the significant advantage of much-reduced multiplier complexity, relative to the direct-form structure. For example, when look-ahead pipelining is not employed and for polyphase architectures having two, three, and four phases, the corresponding reductions in multiplier complexity are 20%, 28.6% and 33.3%, respectively. A proof-of-concept prototype circuit is designed and implemented on a Xilinx Sx35 FPGA device for the two-phase case, operating at a frame-rate of 132 million linear frames per second on the uniform linear array (ULA), corresponding to 2-frames-per-clock-cycle at a circuit clock frequency of 66 MHz. The circuit is optimized for low critical path delays (CPDs) using look-ahead pipelining of order three. For ultra-wideband (UWB) radio-frequency (RF) implementations, in such fields as radio astronomy, radar and wireless communications, custom VLSI versions of the proposed circuits are required.     

Fast Implementation of 3-D Digital Filters Via Systolic Array Processors

In this paper a fast implementation architecture of three-dimensional (3-D) FIR or IIR digital filters via systolic VLSI array processors is described. The modular structure presented is comprised of similar processing elements in a linear cascade configuration with local interconnections. High speed throughput rates are attained due to high concurrency, which is achieved by exploiting both pipelining and parallelism. The considered 3-D FIR and IIR filters may be used for the processing of reconstructed 3-D images and in medical imaging applications.     

A Systolic Array 2-D IIR Broadband RF Beamformer

A systolic architecture is proposed for the real-time implementation of broadband 2-D IIR beam filters having applications in ultra-wideband (UWB) radio frequency (RF) antenna arrays. Real-time throughputs of one-frame-per-clock-cycle are achieved. A finite-difference time-domain computational electromagnetic model of a typical indoor propagation environment is used to illustrate that the method significantly reduces the bit error rate of the simulated communication system in the presence of multi-user interference, thereby demonstrating the potential application of the architecture in RF communications.      

3-D IIR filtering using decimated DFT-polyphase filter bank structures

Two three-dimensional (3-D) under-decimated uniform discrete Fourier transform polyphase filter bank structures are proposed along with two applications: first, the sub-pixel motion discrimination of two-dimensional spatial objects moving with approximately constant local velocity in a noisy 3-D spatio-temporal image sequence and, second, the selective filtering of 3-D spatio-temporal broad-band plane waves based on their directions of arrival. The desired 3-D filter passband shapes are realized utilizing combinations of highly selective first-order 3-D infinite-impulse response frequency-planar filters in each band between the analysis and synthesis sections. Measured spatio-temporal performance confirms the high-quality broad-band transmission of passband signals, high directional selectivity and low computational complexity.     

A new 2-D systolic digital filter architecture without global broadcast

In this paper, we propose two-dimensional (2-D) systolic-array infinite-impulse response (IIR) and finite-impulse response (FIR) digital filter architectures without global broadcast, by the hybrid of a modified reordering scheme and a new systolic transformation. This architecture has local broadcast, lower-quantization error, and zero latency without sacrificing the number of multipliers, as well as delay elements under the satisfactory critical period. Furthermore, we extend this new architecture to a useful 2-D systolic cascade-form architecture and provide the comprehensive error analysis for the proposed architectures.     

A 4-D Dual-Fan Filter Bank for Depth Filtering in Light Fields

A light field is a four-dimensional (4-D) representation of the light permeating a scene-it parameterizes light rays as a function of position and direction. Such a structure can be measured using a specialized camera and can be used to render novel views of the scene it represents. It has previously been shown that the light field model of a scene may be filtered for a single depth by employing frequency-planar filters. Here, we show how a light field may be selectively filtered for a range of depths by forming a 4-D frequency passband that surrounds the intersection of two 4-D fans. A newly proposed cascaded filter bank is shown to approximate this passband, and its effectiveness is demonstrated on two scenes, both of which contain occlusions. Results are compared with those previously obtained using 4-D frequency-planar filters     

A new class of two-channel biorthogonal filter banks and waveletbases

Proposes a novel framework for a new class of two-channel biorthogonal filter banks. The framework covers two useful subclasses: i) causal stable IIR filter banks. ii) linear phase FIR filter banks. There exists a very efficient structurally perfect reconstruction implementation for such a class. Filter banks of high frequency selectivity can be achieved by using the proposed framework with low complexity. The properties of such a class are discussed in detail. The design of the analysis/synthesis systems reduces to the design of a single transfer function. Very simple design methods are given both for FIR and IIR cases. Zeros of arbitrary multiplicity at aliasing frequency can be easily imposed, for the purpose of generating wavelets with regularity property. In the IIR case, two new classes of IIR maximally flat filters different from Butterworth filters are introduced. The filter coefficients are given in closed form. The wavelet bases corresponding to the biorthogonal systems are generated. the authors also provide a novel mapping of the proposed 1-D framework into 2-D. The mapping preserves the following: i) perfect reconstruction; ii) stability in the IIR case; iii) linear phase in the FIR case; iv) zeros at aliasing frequency; v) frequency characteristic of the filters     

A technique for realizing linear phase IIR filters

A real-time IIR filter structure is presented that possesses exact phase linearity with 10~1000 times fewer general multiplies than conventional FIR filters of similar performance and better magnitude characteristics than equiripple or maximally flat group delay IIR filters. This structure is based on a technique using local time reversal and single pass sectioned convolution methods to realized a real-time recursive implementation of the noncausal transfer function H(z^-1). The time reversed section technique used to realize exactly linear phase IIR filters is described. The effects of finite section length on the sectional convolution are analyzed. A simulation methodology is developed to address the special requirements of simulating a time reversed section filter. A design example is presented, with computer simulation to illustrate performance, in terms of overall magnitude response and phase linearity, as a function of finite section length. Nine example filter specifications are used to compare the performance and complexity of the time reversed section technique to those of a direct FIR implementation     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

Design methodology for subdigit pipelined digit-serial IIR filters

A novel architecture for high performance two's complement digit-serial IIR filters is presented. The application of the digit-serial computation to the design of IIR filters introduces delay elements in the feedback loop of the IIR filter. This offers the possibility of pipelining the feedback loop inherent in the IIR filters. To fully explore the advantages offered by the use of digit-serial computation, the digit serial structure is based on the feed forward of the carry digit, which allows subdigit pipelining to increase the throughput rate of the IIR filters. A systematic design methodology is presented to derive a wide range of digit-serial IIR filter architectures which can be pipelined to the subdigit level. This will give designers greater flexibility in finding the best trade off between hardware cost and throughput rate. It is shown that the application of digit-serial computations for the realisation of IIR filters combined with the possibility of subdigit pipelining, results in an increase in the computation speed with a considerable reduction in silicon area consumption when compared to an equivalent bit-parallel IIR filter realisations.     

Design of 1-D Stable Variable Fractional Delay IIR Filters

In this brief, a two-stage approach for the design of 1-D stable variable fractional delay infinite-impulse response (IIR) digital filters is proposed. In the first stage, a set of fixed delay stable IIR filters are designed by minimizing a quadratic objective function, which is defined by integrating error criterion with IIR filter stability constraint condition. Then, the final design is determined by fitting each of the fixed delay filter coefficients as a 1-D polynomial. Two design examples are given to show the effectiveness of the proposed design method     

On Analog Networks and Mixed-Domain Spatio-Temporal Frequency Response

In this paper, we extend the linear cellular neural network (CNN) paradigm by introducing temporal derivative diffusion connections between neighboring cells. Our proposal results in an analog network topology for implementing general continuous-time discrete-space mixed-domain 3-D rational transfer functions for linear filtering. The network connections correspond one-to-one to the transfer function coefficients. The mixed-domain frequency response is treated as a temporal frequency-dependent spatial function and we show how nonseparable properties of the spatio-temporal magnitude response can be derived from the combination of: 1) sinusoidal functions of spatial frequencies and 2) polynomials of the continuous-time frequency in the 3-D frequency response expression. A generic VLSI-compatible implementation of the network based on continuous-time integrators is also proposed. Based on our proposed CNN extension, the analysis of a spatio-temporal filtering example originated from analytical modeling of receptive fields of the visual cortex is presented and a spatio-temporal cone filter is designed and presented with numerical simulation results.      

A novel 5-D depth–velocity filter for enhancing noisy light field videos

A 5-D depth–velocity filter is proposed for enhancing moving objects in noisy light field videos (LFVs) (also known as plenoptic videos). The proposed filter consists of an ultra-low complexity 5-D IIR depth filter and a 5-D FIR velocity filter. The 5-D IIR depth filter is employed to denoise a noisy LFV. The denoised LFV is then utilized to estimate the 3-D apparent velocity of the moving object of interest. The 5-D FIR velocity filter is designed based on the estimated 3-D apparent velocity and is used to enhance the moving object of interest while attenuating other interfering moving objects. Experimental results confirm the effectiveness of the proposed 5-D depth–velocity filter compared to previously reported 5-D depth–velocity filters.     

Frequency domain design of FIR and IIR Laplacian of Gaussian filters for edge detection

This work addresses the design of LoG filters in the frequency domain within a structure formed by the cascade of quasi-Gaussian and discrete Laplacian filters. The main feature of such a structure is that it requires half the number of convolutions of the classical structure in which the LoG transfer function is expressed as the sum of two separable transfer functions of 1-D Gaussian and LoG type. Such a perspective allows one to rephrase the design of IIR and FIR filters for edge detection as a frequency domain approximation problem solvable by standard digital filter design tools. The zero-phase IIR solutions have a good performance at low orders and approximation errors practically independent of the aperture parameter. The characteristics of the nearly linear-phase IIR filters solving the problem suggest the consideration of linear-phase FIR filters with zeros constrained on the unit circle. The use of such filters leads to remarkable computational savings with respect to the filters designed by impulse response sampling. The agreement between the edge values obtained by the filters designed according to the scheme proposed in this work and those obtained by standard techniques is very good.Work carried out with the financial support of the C.N.R.-Progetto Finalizzato Robotica, contract no. 91.01942.PF67.     

A parallel 3-D discrete wavelet transform architecture using pipelined lifting scheme approach for video coding

This article presents a parallel architecture for 3-D discrete wavelet transform (3-DDWT). The proposed design is based on the 1-D pipelined lifting scheme. The architecture is fully scalable beyond the present coherent Daubechies filter bank (9,?7). This 3-DDWT architecture has advantages such as no group of pictures restriction and reduced memory referencing. It offers low power consumption, low latency and high throughput. The computing technique is based on the concept that lifting scheme minimises the storage requirement. The application specific integrated circuit implementation of the proposed architecture is done by synthesising it using 65?nm Taiwan Semiconductor Manufacturing Company standard cell library. It offers a speed of 486?MHz with a power consumption of 2.56?mW. This architecture is suitable for real-time video compression even with large frame dimensions.     

A sample-and-hold semi-systolic analogue realization for 2-D recursive digital filters

A sample-and-hold semi-systolic analogue realization for 2-D IIR niters utilizing only analogue components (analogue multipliers, CCDs, ?, etc.) is presented. This form of realization would be capable of handling the high data rate required by such applications as high definition television (HDTV) (? 1050 × 1400 pixels per frame). Such applications would require a throughput rate in excess of 40 million pixels per second.

Available forms of digital realizations for 2-D IIR filters are incapable of achieving such a high rate with commercially available ICs and/or realistic cost.     

Electronically scanned RF-to-bits beam aperture arrays using 2-D IIR spatially bandpass digital filters

A beamforming system based on two-dimensional (2-D) spatially bandpass infinite impulse response (IIR) plane wave filtering is presented in a multi-dimensional signal processing perspective and the implementation details are discussed. Real-time implementation of such beamforming systems requires modeling of computational electromagnetics for the antennas, radio frequency (RF) analog design aspects for low-noise amplifiers (LNAs), mixed-signal aspects for signal quantization and sampling and finally, digital architectures for the spatially bandpass plane wave filters proposed in Joshi et al. (IEEE Trans Very Large Scale Integr Syst 20(12):2241–2254, 2012). Multi-dimensional spatio-temporal spectral properties of down-converted RF plane wave signals are reviewed and derivation of the spatially bandpass filter transfer function is presented. An example of a wideband antipodal Vivaldi antenna is simulated at 1 GHz. Potential RF receiver chains are identified including a design of a tunable combline microstrip bandpass filter with tuning range 0.8–1.1 GHz. The 1st-order sensitivity analysis of the beam filter 2-D $\mathbf z $ -domain transfer function shows that for a 12-bits of fixed-point precision, the maximum percentage error in the 2-D magnitude frequency response due to quantization is as low as $0.3\,\%$ . Monte-Carlo simulations are used to study the effect of quantization on the bit error rate (BER) performance of the beamforming system. 5-bit analog to digital converter (ADC) precision with 8-bit internal arithmetic precision provides a gain of approximately 16 dB for a BER of $10^{-3}$ with respect to the no beamforming case. ASIC Synthesis results of the beam filter in 45 nm CMOS verifies a real time operating frequency of 429 MHz.     

Design of 3-D Noncausal Filters with Small Roundoff Noise and No Overflow Oscillations

The contribution of this paper consists of two individual parts. First, an invertible mapping technique is presented for 3-D digital system design, and it is applied to approximate 3-D noncausal filters in the spatial domain. Secondly, an algorithm is proposed for obtaining a structure for 3-D IIR filters with small roundoff noise and no overflow oscillations. The design of noncausal filters can be carried out by three steps: 1), a given noncausal impulse response is transformed into the first octant using the proposed 3-D invertible mapping technique; 2), the transformed impulse response in the first octant is approximated by balanced model reduction of 3-D separable denominator systems;3), the resultant 3-D IIR filter is transformed back to the original coordinates.