共查询到19条相似文献,搜索用时 140 毫秒
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基于FPGA的精密时间间隔测量仪设计 总被引:1,自引:1,他引:0
介绍一种基于FPGA的精密时间间隔测量仪的研制过程。精密时间间隔测量仪是应科学试验中高可靠性、高精密度和多通道等测量要求而研制的。精密时间间隔测量仪以PXI接口为平台设计成为虚拟仪器,一个PXI系统可插多个精密时间间隔测量仪板卡,每个板卡可对1个起始通道与8个停止通道的脉冲信号进行时间间隔测量,同时测量停止脉冲的脉冲宽度。精密时间间隔测量仪以FPGA为测时核心,利用锁相环倍频和时钟分相技术,测量分辨力可达到1ns,测时范围可达10ns-10ms。 相似文献
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一种高精度时间间隔测量方法及仿真验证 总被引:1,自引:0,他引:1
在分析当前获得广泛应用的时间间隔测量方法的基础上,提出了一种时间-相位转换方法,该方法相对传统方法具有十分明显的优点,时间间隔测量精度理论上能够达到皮秒量级,并给出基于该方法的高精度时间间隔测量仪的实现原理框图,最后给出仿真结果. 相似文献
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介绍了通用时间间隔计数器SR620和时间间隔分析4~E1725C的测量原理,并对其测试能力进行了比较。 相似文献
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基于CPLD和89S51的多功能信号测量仪 总被引:1,自引:0,他引:1
提出一种基于CPLD和89S51的多功能信号测量仪,该测量仪可测量频率,周期和脉宽等参数.介绍了高精度测频方法、可编程逻辑器件应用以及周期脉宽测量方法.以CPLD和单片机为核心,消除了直接测频方法对测量频率需采用分段测试的局限性,该多功能信号测量仪可在整个测试频段内保持高精度,测量频率范围达0.1Hz~100MHz以上. 相似文献
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时间间隔的测量精度对脉冲激光测距系统的测量精度起决定作用.为此研制了一高精度时间间隔测量模块,该模块基于专用时间数字转换芯片开发,采用延迟线插入法技术,最大测量时间可高达200ms,测时分辨率最高可达125ps,对应测距分辨率18.75mm,适用于远距离的测量.给出了硬件和软件设计方法以及模块的测试结果. 相似文献
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天线远场测量是获得其辐射特性的一种常用方法,为得到方向图的细节,测量方向图的角度间隔一般应小于待测天线半功率波束宽度的1/10,否则会导致方向图相关参数如半功率波束宽度、副瓣电平等的不准确. 针对高增益、窄波束天线的远场测量,为了得到精确测量结果,测量间隔要求非常小,导致测试时间长,测试效率低下. 文中提出了一种基于带限周期函数的Fourier插值法的高效率方向图测试方法,此方法将采样间隔增加到待测天线半功率波束宽度量级,仍然可以准确重构出角度间隔任意小的方向图,从而能够显著提高测试效率. 仿真和实测结果证明了本方法的可行性. 相似文献
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光子计数成像激光雷达时间间隔测量系统研究 总被引:9,自引:3,他引:6
光子计数成像激光雷达需要测量一个激光主波和与之对应的多个回波之间的时间间隔,并具有高精度.采用延迟线插入法时间间隔测量技术,研制了具有27ps分辨率的多脉冲时间间隔测量系统,介绍了系统的软硬件结构及工作流程,测试了精度和线性度等指标,实验结果表明系统精度达到80ps,线性度良好. 相似文献
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Richardson Charles Orman Steven S. Humphrey Gordon L. 《IEEE transactions on bio-medical engineering》1977,(2):199-201
A low-cost TTL counter with a selectable time gate is described. A manual or an external trigger initiates the time-gated counting cycle. Included in the circuitry is a variable trigger delay and a test circuit that allows display of the clock signal. The counter has applications in neurophysiology including counting units for a predetermined time interval. 相似文献
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本文针对采用跳频数传TDMA接入的Ad hoc网络,提出了一种利用跳频同步来实现TDMA时隙同步的方案。考虑到时隙同步是为了使得各个节点的时隙基准对齐,并不需要保持节点之间具体时间一致,利用跳频同步采用分隔符对跳频帧的定位,对定位进行时延补偿后,可实现时间基准基本对齐。由于同步偏差的存在,通过设置保护带允许时隙的抖动来防止冲突发生。本文给出了具体的同步实现方案,并且与其他的Ad hoc网络时隙同步方案进行了比较。仿真结果表明,该方案占用了较少的传输带宽,提高了效率,并且可以保证一定的同步精度。 相似文献
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Jansson J.-P. Mantyniemi A. Kostamovaara J. 《Solid-State Circuits, IEEE Journal of》2006,41(6):1286-1296
A high-precision CMOS time-to-digital converter IC has been designed. Time interval measurement is based on a counter and two-level interpolation realized with stabilized delay lines. Reference recycling in the delay line improves the integral nonlinearity of the interpolator and enables the use of a low frequency reference clock. Multi-level interpolation reduces the number of delay elements and registers and lowers the power consumption. The load capacitor scaled parallel structure in the delay line permits very high resolution. An INL look-up table reduces the effect of the remaining nonlinearity. The digitizer measures time intervals from 0 to 204 /spl mu/s with 8.1 ps rms single-shot precision. The resolution of 12.2 ps from a 5-MHz external reference clock is divided by means of only 20 delay elements. 相似文献
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用于多点测试的全光纤速度干涉仪研究 总被引:2,自引:1,他引:2
基于时分复用(TDM)原理,提出了一种新型的用于多点速度测试的全光纤干涉系统,通过同一个冲击靶面的测速实验验证方案的可行性。该系统通过在原有全光纤速度干涉仪(AFVI)的探测端口引入光纤耦合器和延迟线,由于延时的存在,被测点干涉信号之间在时间上存在相同的延时,利用时分复用原理,能够实现以往需要多套速度干涉仪才能实现的对测试靶面的多点测试功能。通过对同一个测试自由面上的两点进行测试,得到了具有一定时延的相似干涉条纹,而且延迟的时间与光纤延迟线对应。实验验证了系统设计的正确性。 相似文献
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A low-power CMOS time-to-digital converter 总被引:1,自引:0,他引:1
Raisanen-Ruotsalainen E. Rahkonen T. Kostamovaara J. 《Solid-State Circuits, IEEE Journal of》1995,30(9):984-990
A time-to-digital converter, TDC, with 780 ps lsb and 10-μs input range has been integrated in a 1.2-μm CMOS technology. The circuit is based on the interpolation time interval measurement principle and contains an amplitude regulated crystal oscillator, a counter, two pulse-shrinking delay lines, and a delay-locked loop for stabilization of the delay. The TDC is designed for a portable, low-power laser range-finding device. The supply voltage is 5±0.5 V, and the operating temperature range is -40 to +60°C. Single-shot accuracy is 3 ns and accuracy after averaging is ±120 ps with input time intervals 5-500 ns. In the total input range of 10 μs, the final accuracy after averaging is ±200 ps. Current consumption is 3 mA, and the chip size is 2.9 mm×2.5 mm 相似文献
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Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique.Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.This work was funded in part by Sandia National Laboratory under contract SANDIA-27-6108. 相似文献
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以STM32F103VET6微控制器作为系统控制核心,在对光照时间、延迟时间、脉冲采集时间精确控制的基础上,选取止度较深、波长控制精确的滤光片,配合单光子计数器,设计一套基于微控制器的生物延迟发光光谱探测系统。对小麦延迟发光光谱进行探测,测试结果表明:小麦延迟发光强STM32要集中在波长525 nm以上,且在640 nm附近存在明显峰值。 相似文献