高温老化工艺在电子元器件老化测试工作中的应用

在现代电子产品的制造和设计过程中,元器件的可靠性和使用寿命是至关重要的因素。为了评估元器件在极端条件下的表现,高温老化工艺成为一种重要的测试手段。因此,本文探讨了高温老化工艺在电子元器件老化测试工作中的应用。旨在通过对电子元器件在高温环境中的性能变化以及可靠性退化进行模拟,帮助制造商评估产品的寿命、性能和适应性。在文章中,实验测试记录了性能参数的变化、失效率分析、老化曲线和性能稳定性评估的实验结果,以展示高温老化工艺在测试中的重要作用。     

基于PSpice的恒流源设计与实现

测量系统中常需要交流恒流源作为系统的校准、标定信号源。本文在充分搜集、整理和分析各种恒流电路的基础上,设计了一个压控交流恒流放大系统。该电路系统由恒流放大级、功率推动级及中点伺服电路三级构成,具有恒流特性较好、反馈电阻可调的优点。在设计过程中,先用PSpice进行仿真,然后进行实际电路的制作和测试,验证了该系统的有效性。     

一种基于模糊监督协调控制的保护装置测试方法

机车保护装置种类繁多, 测试时需要提供各种波形的大电流, 且要求电流具有特定的脉动, 现有的测试设备已难以满足测试与故障诊断要求。针对测试对象多样、时变, 常规控制方法难以实现的状况, 提出基于模糊监督协调控制的系统控制策略。设计自适应PID相位控制器对恒流或曲线模式下的相位进行控制, 配合神经网络控制器在线学习, 实现准确快速的控制。测试系统的实际投入使用与专家技术鉴定表明, 该方法有效地提高了测试效率与准确性。     

面向进水电磁阀性能测试的恒压恒流供水系统设计

针对洗衣机及洗碗机进水电磁阀性能检测中的多级水压控制问题,首先介绍电磁阀性能测试流程,根据电磁阀性能测试要求进行恒压恒流供水系统设计。通过分析恒压恒流供水系统原理,设计出恒压控制电路、恒流控制电路、霍耳型流量传感器信号检测电路及控制流程,最后对恒压恒流供水系统进行应用实验。实验结果表明：恒压恒流调节控制快速,且调节后预置值与实际值误差较小,可以满足各种水压、水流量测试要求。     

氦氖激光器电源的调流控制方法研究

针对氦氖激光器加速寿命试验对电流控制的要求,设计了一种简单、高效的调流控制电路,该电路具有调流范围宽、恒流效果好的特点。试验结果表明,该设计满足加速寿命试验系统对电流控制的要求,可以应用于加速寿命试验系统。     

基于Matlab的多通道热敏电阻老化测试系统

该套测试系统旨在解决现存热敏电阻老化测试中,测试温度环境不稳定,测试过程需大量人工干预,测量结果精度不高等问题。该系统可同时对50路样本进行测量,采用具有温度波动度小于0.2℃的精密恒温水槽为测试提供稳定可靠的高低温恒温环境,由气缸级联而成的"机械手臂"代替手工操作,依靠下位机高精度测量模块实现相对误差小于0.5%的电阻测量,利用Matlab编写的上位机软件绘制R-t曲线分析样本老化特性,实际应用表明,整套测试平台稳定可靠、测量准确、自动化程度高,极大地提高了生产效率。     

程控隔离恒流电源在仪器仪表中的应用

0　引言在实际应用中 ,许多地方需要有一个恒定的电流提供电源【1】。例如 ,测量某确定电流点上二极管的正、反向电压 ;测试某恒定基极电流时三极管的输出特性 ;可充电电池的恒流充电、各类传感器的恒流供电等。在各类电子仪器和测试系统中 ,恒流电源也得到了广泛的应用。如在电机的型式试验中 ,有一个重要的试验项目即温升试验 ,它表明电机在特定的工作状态下温度的上升速率和程度。电机的温升通常是通过测量其绕组的冷、热态电阻来获得的【2】。采用电阻法测量绕组电阻时 ,就需要一组高精度、高稳定性的直流恒流电源。电机热态电阻的理想…     

高功率因数LED恒流可调驱动电源设计

分析具有PFC的反激式隔离型AC/DC的LED恒流驱动电源的设计方法。给出高效率和高功率因数条件下隔离高频变压器以及由UCC28810构成的功率因数校正电路的具体设计方案和相关参数的选择方法;阐述了由CC2530和SN3350构成的PWM恒流可调电路的工作原理。通过对实验样机在输入电压90 V~260 V范围内进行多样实验测试取均值结果表明,系统的功率因数均值在0.97以上,AC/DC变化电路的效率高达86.5%;恒流模块的效率达到93.2%,实现恒流可控的PWM的调光功能。     

电子元器件老化测试系统的研制

针对电子元器件可靠性问题设计了电子元器件老化测试系统,实现在仿真的温度环境下对电子元器件进行老化测试,自动检测出元器件潜在故障缺陷,保证电子产品良好的加工质量与可靠性,为改进生产工艺和提高产品质量提供有效保障。     

泛华恒兴推出电子节气门(ETC)耐久测试台

<正>致力于为各行业用户提供高品质测试测量解决方案和成套检测设备的北京泛华恒兴科技有限公司(简称:泛华恒兴)近日推出了电子节气门(ETC)耐久测试台。该产品可用于温度环境下的性能耐久测试,并广泛用于实验室和生产线的ETC电子节气门测试。该系统属于ETC实验室耐久类设备,通过上位机软件可预先设定ETC寿命曲线,根据采集的ETC传感器输出     

基于光谱吸收式光纤乙炔气体监测系统的研

选用分布反馈式半导体激光器(DFB LD)作为激发光源,带尾纤的气体吸收气室作为传感器的探测头,以及锁相放大器来提取信号,并通过谐波检测技术对所提取的微弱信号进行处理,设计了一套远距离在线测量乙炔气体的监测仪器.经过理论分析和系统实验,表明系统设计方案可行,具有较高的精度和一定的应用前景.     

T/R组件电老练测试系统设计

T/R组件电老练测试系统主要用于T/R组件的研制和生产。针对T/R组件电老练测试过程中工作量大、耗时长的问题,提出了一种可批量电老练的组合式T/R组件电老练测试系统解决方案,对电老练测试系统进行了开发验证。设备为组合机柜式结构,功能上分为电老练单元区、电源仪表区和人机交互区,可实现T/R组件在预设条件(供电、射频、脉冲和温度等)下规定时长的电老练测试。测试软件是基于自适应调节控制算法的并行测试技术实现电老练自动测试管理,并基于IVI技术进行仪器仪表的控制接口封装,实现24通道T/R组件产品老练过程中的实时数据采集、处理、显示、存储功能。系统采用模块化结构,可根据需要灵活配置;软件平台界面接口丰富、开放程度高,具备良好的维护性和拓展性。实际应用表明此系统满足T/R组件电老练测试各项指标要求;与传统方法相比,自动化程度高,能够较大程度地提高T/R组件电老练测试效率,具备较强的实用性。     

Component reliability improvement through rejection by nondestructive testing and burn-in

The paper examines mathematical models of component reliability improvement through rejection by nondestructive testing and burn-in. Component reliability models allowing for the manufacturing process are considered.Translated from Kibernetika i Sistemnyi Analiz, No. 3, pp. 73–84, May–June, 1992.     

Reducing burn-in time through high-voltage stress test and Weibull statistical analysis

To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.     

使用可视化编程语言实现EMS测试的闭环控制

随着人类生活空间电磁环境的日益恶化,人们对电磁兼容性自动检测有着迫切要求。本文介绍在VB环境下GTEMC（吉兆赫横电磁波小室）EMS闭环自动测试系统的设计原理及具体的实现方法。     

弹载指令设备自动老炼试验系统设计

针对导弹弹载指令设备可靠性试验周期长、人员工作负荷高的现状和型号研制效率需求,设计了一种以工控机为硬件核心、LabVIEW为软件开发平台的自动老炼试验系统,实现整个试验过程的自动控制、数据采集与处理、故障诊断与处理及数据保存与实时显示等功能,并以某型导弹弹载指令设备为实例,验证了试验系统的性能.应用表明,该自动老炼试验系统操作简便、工作稳定,降低了测试人员的工作强度,提高了试验效率和自动化水平,大大提升了型号交付进度.     

Test and reliability: partners in IC manufacturing. 2

This article discusses the major gate oxide failure modes, reliability modeling, burn-in, and qualification testing. We present a typical method to calculate failure rates     

Minimizing makespan on a single burn-in oven with job families and dynamic job arrivals

This paper considers a scheduling problem for a single burn-in oven in the semiconductor manufacturing industry where the oven is a batch processing machine and each batch processing time is represented by the largest processing time among those of all the jobs contained in the batch. Each job belongs to one of the given number of families. Moreover, the release times of the jobs are different from one another. The objective measure of the problem is the maximum completion time (makespan) of all jobs. A dynamic programming algorithm is proposed in the order of polynomial time complexity for a situation where the number of job families is given (fixed). A computational experiment is performed to compare the time complexity of the proposed algorithm with that of another exact algorithm evaluating all possible job sequences based on batching-dynamic programming (BDP). The results of the experiment show that the proposed algorithm is superior to the other.Scope and purposeThis paper considers a scheduling problem on the burn-in operation in a semiconductor manufacturing process. The burn-in operation is a bottleneck process in the final testing process which is one of four major steps including wafer fabrication, wafer probe, assembly, and final testing steps. Thus, its scheduling is very important to improve the productivity of the whole manufacturing line. The objective of this paper is to find a solution technique that will find the optimal schedule that minimizes makespan for problems which are found in the semiconductor manufacturing industry.     

All‐uses testing of shared memory parallel programs

Parallelism has become a way of life for many scientific programmers. A significant challenge in bringing the power of parallel machines to these programmers is providing them with a suite of software tools similar to the tools that sequential programmers currently utilize. Unfortunately, writing correct parallel programs remains a challenging task.In particular, automatic or semi‐automatic testing tools for parallel programs are lacking. This paper takes a first step in developing an approach to providing all‐uses coverage for parallel programs. A testing framework and theoretical foundations for structural testing are presented, including test data adequacy criteria and hierarchy, formulation and illustration of all‐uses testing problems, classification of all‐uses test cases for parallel programs, and both theoretical and empirical results with regard to what can be achieved with all‐uses coverage for parallel programs. Copyright © 2003 John Wiley & Sons, Ltd.     

Wafer Test Methods to Improve Semiconductor Die Reliability

Incremental advances in semiconductor device testing have improved device quality and reliability. New test methods applied to dies at the wafer level are now significantly improving the reliability of devices sold to the increasing bare-die market and reducing burn-in requirements for packaged devices.