低频EoC 64和74系列对比分析及互联互通注意事项

以低频EoC HomeplugAV方案的INT6400互联互通设计为基础,总结了EoC通信领域不同厂家互联互通的设计方案,并进一步分析比较了AR7410方案与INT6400方案的差异,并对两种方案的互联互通给出建议。     

MPEG4音、视频编码芯片IME6400及其应用

IME6400是韩国INTiME公司开发的、可支持MPEG4高分辨率实时视频编码的集成电路芯片。文中介绍了IEM6400芯片的性能特点，给出了利用该芯片设计基于嵌入式PC内核的数字视频监控系统的具体方法。     

INT6400与AR7400芯片EoC共存组网特点分析

随着7400芯片EoC解决方案逐渐被广电市场认可,后期大量基于7400芯片解决方案的EoC将被应用于广电网络中。但是现阶段主要使用的基于INT6400芯片的方案EoC,如果一次性全部更新换代不现实,所以将来的一段时间里6400芯片EoC与7400芯片EoC共存的局面一定会存在,为此利用多个对比测试数据对此组网环境带来的网络影响做简要分析。     

亚太最大的移动联盟启动区域性移动服务

将有超过6400万的用户享受到无缝的海外漫游服务。     

至强双核工作站提升计算与图形处理能力

HP(惠普)日前发布了旗下个人工作站家族两名新成员—HP Workstation xw6400和xw8400。HP亚太及日本地区信息产品与商用渠道集团(PSG)工作站部门副总裁Li Li Chung说：“这两款全新的台式HP xw6400和xw8400工作站采用了最新的Intel双核至强处理器,带来了最新一代的技术创新,可为用户提供更出色的计算性能和     

植物延迟荧光与光合能力相关性的理论与实验研究

从理论推导出利用延迟荧光强度表征光合能力的相关条件及数学模型,以玉米叶片和紫薇叶片为样品,用自制的延迟荧光探测系统与光合速率测量仪LI-6400进行了延迟荧光强度与光合速率的对比测量.实验结果表明,两者具有良好的线性相关性,与理论推导的结果一致;延迟荧光测量时间在10 s内,而LI-6400的稳定测量结果需要5～10 min.因此,延迟荧光技术是一种快速、准确的表征植物光合能力的方法.     

台商新品

采用Intel Core 2 Duo E6400工业用主机板Kontron推出新一代采用Kontron Intel Core 2 Duo E6400处理器工业用主机板KT965/FLEX。这款工业用主机板采用Intel Q965 Express芯片组。Intel Core 2 Duo处理器系列提供约增加40%的应用效能和40%的较低功耗。新的Intel Q965 Express芯片组拥有FSB 1,066MHz的性能。而Intel宽广的动态执行,也是Intel核心微型架构的特性,采用四个并     

喇曼光谱仪

英国Instrument SA责任有限公司生产一种T6400型科研用喇曼光谱仪,它采用三个单元集成的结构设计方案,可以去掉,加上     

F&K 6400键合机在SMD封装中的应用

键合是SMD封装中的一道重要工序,F&K 6400键合机是德国F&K公司专门面向细铝丝键合的设备,采用超声作为键合能量。在键合工艺中不同材质的金属管座会形成不同的冶金系统,有些情况下会造成接触面腐蚀或者柯肯德尔空洞,并最终影响产品的可靠性。键合时采用的超声功率、键合时间、键合压力、键合方式等工艺参数直接影响到产品的产量和性能。在批量生产的基础上,作者分析了适合F&K 6400键合机在生产中采用的键合材料及工艺参数,并列出了生产过程中设备常见的故障及可能原因。     

“芯芯相映，成就激情”——HP发布基于英特尔至强双核处理器的台式工作站新品

2006年6月29日惠普（HP）在北京发布了放下个人工作站家族两名新成员——HP Wotkstatictl xw6400和xw8400。这两款全新的台式HP xw6400和xw8400工作站采用最新的双核英特尔至强处理器．带来了最新一代的技术创新，可为用户提供更出色的计算性能和更强大的图形处理能力．从而进一步巩固了惠普作为业界拥有最广泛的双核工作站产品的厂商地位。     

基于USB 2.0的AV数字采集系统的设计

AV信号的采集和通过网络快速的传输在现实生活中得到越来越广泛的应用，具有高压缩率的MPEG4标准很好地满足了人们的这一需求，而USB技术因其即插即用的方便特性也得到了普遍的应用，因此二者的结合是一个必然的选择。本文介绍了一种基于USB2．0接口的AV数字采集系统的设计方案及其软件设计方法。该系统使用了1NTIME公司的IME6400芯片，其内部集成了存放代码的ROM，降低了系统实现的成本。他可以生成MPEG4／2／1传输流，所以本系统可以满足交互AV服务和远程监控的需要。     

基于ARM9的嵌入式多路视频监控系统设计

介绍一种基于ATMEL公司ARM9微处理器AT91RM9200的嵌入式多路视频监控系统方案。系统以嵌入式Linux操作系统为平台,采用TECHWELL公司的TW2834芯片对4路视频进行A／D转换,然后通过IMTIME公司MPEG-4的专用编码芯片IME6500对采集到的多路视频信号进行压缩编码,生成MPEG-4视频流。     

基于ARM11电力载波视频监控服务器设计与实现

针对视频监控架设受环境和空间影响,视频数据线布线复杂与布线成本较高的问题。设计了一种基于电力载波的视频监控服务器,采用嵌入式处理器S3C6410作为控制核心,INT6400和INT1400组成电力载波传输模块,传输视频信号。该服务器具有体积小、功耗低、安装方便等优点,有广阔的市场应用前景。     

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

Motion estimation (ME) is the most critical component of a video coding standard. H.264/AVC adopts the variable block size motion estimation (VBSME) to obtain excellent coding efficiency, but the high computational complexity makes design difficult. This paper presents an effective processor chip for integer motion estimation (IME) in H264/AVC based on the full-search block-matching algorithm (FSBMA). It uses architecture with a configurable 2D systolic array to obtain a high data reuse of search area. This systolic array supports a three-direction scan format in which only one row of pixels is changed between the two adjacent subblocks, thus reducing the memory accesses and saving clock cycles. A computing array of 64 PEs calculates the SAD of basic 4×4 subblocks and a modified Lagrangian cost is used as matching criterion to find the best 41 variable-size blocks by means of a tree pipeline parallel architecture. Finally, a mode decision module uses serial data flow to find the best mode by comparing the total minimum Lagrangian costs. The IME processor chip was designed in UMC 0.18 μm technology resulting in a circuit with only 32.3 k gates and 6 RAMs (total 59kBits on-chip memory). In typical working conditions (25 °C, 1.8 V), a clock frequency of 300 MHz can be estimated with a processing capacity for HDTV (1920×1088 @ 30 fps) and a search range of 32×32.     

Parallel spiral search algorithm applied to integer motion estimation

Thanks to its flexible coding structure, high-efficiency video coding (HEVC) can save more coding bit rates than the previous standard, H.264. However, it also increases the complexity of integer-pixel motion estimation (IME). To speed up the encoding process, we propose a parallel spiral search (PSS) algorithm, which features the following characteristics and advantages. First, the proposed algorithm is hardware-friendly. PSS has both a fix search order that cuts the correlation between search points and a high data reuse level that facilitates the pipeline application in hardware implementation. Second, the PSS algorithm processes all prediction units (PU) blocks in parallel, which speeds up the RD calculation. Finally, the early termination strategy is proposed to end the search for unnecessary search points and further reduce search time. Experimental results show that the proposed algorithm outperforms other popular hardware-oriented IME algorithms in terms of coding speed, with the same loss of RD performance. Compared with the default full search algorithm (FSA) in the HEVC test model HM-16.7, the proposed algorithm achieves average time saving ratio of up to 92.55%, with BD-PSNR loss of 0.056 dB and an increase by 1.38% in terms of BD-BR.     

A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video

Motion estimation (ME) in high-definition H.264 video coding presents a significant design challenge for memory bandwidth, latency, and cost because of its large search range and various modes. To conquer this problem, this paper presents a low-latency and hardware-efficient ME design with three design techniques. The first technique on integer-pel ME (IME) adopts parallel instead of serial multiresolution search so that we can process 1080 p @ 60 fps videos with $pm$128 search range within just 256 cycles, 5.95-KB buffers, and 213.7K gates. The second technique on fractional-pel ME (FME) uses a single-iteration six-point search to reduce the cycle count by half with similar gate count and negligible quality loss. The third technique applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME. The final ME implementation with 0.13-$mu{hbox {m}}$ process can support processing of 1080 p @ 60 fps with just 128.8 MHz, 282.6 K gates, and 8.54-KB buffer, which saves 60% gate count, and 68.9% SRAM buffers when compared with the previous design.      

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

运用VLC媒体播放器增加HDTV播出频道的实践

VLC是一个开放源代码的、跨平台的多媒体播放器,它可以播放多种音频和视频格式(MPEG-1、MPEG-2、MPEG-4、D ix、MP3、Ogg等以及DVD、VCD、CD音频以及各种流媒体协议),VLC同时也具有转码能力(UDP unicast和multicas、tHTTP等),主要为宽带网络设计的流媒体服务器使用。基于上述软件,结合拥有G igabitEthernet I/O板卡的统计复用网关DM6400、复用/加扰/调制器BN G6104和播发服务器、HDTV机顶盒,试验播出2个HDTV频道。     

Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder

Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critical issue. Data reuse (DR) is a technique that recycles the data read from memory and can be used to reduce memory access power. In this paper, a systematic method of DR exploration for low-power architecture design is presented. For a start, the signal processing algorithms should be formulated as the nested loops structures, and data locality is explored by use of loop analysis. Then, corresponding DR techniques are applied to reduce memory access power. The proposed design methodology is applied to the motion estimation (ME) algorithms of H.264 video coding standard. After analyzing the ME algorithms, suitable parallel architectures and processing flows of the integer ME (IME) and fractional ME (FME) are proposed to achieve efficient DR. The amount of memory access is respectively reduced to 0.91 and 4.37% in the proposed IME and FME designs, and thus lots of memory access power is saved. Finally, the design methodology is also beneficial for other signal processing systems with a low-power consideration.