高速BiCMOS工艺研究

研究开发一种准２μｍ高速ＢｉＣＭＯＳ工艺，该工艺采用乍对准双埋双阱及外延结构。外延层厚度２．０－２．５μｍ，器件间采用多晶硅缓冲层局部氧化隔离，双极器件采用多晶硅发射极晶体管。利用此工艺试制出ＢｉＣＭＯＳ２５级环振，在负载电容ＣＬ＝０．８ｐＦ条件下，平均门延迟时间ｔｑｄ＝０．８４ｎｓ，功耗为０．３５ｍＷ／门，驱动能力 ０．６２ｎｓ／ｐＦ，明显ＣＭＯＳ门。     

双多晶硅栅SOI MOS器件的研究

采用多晶硅栅全耗尽ＣＭＯＳ／ＳＩＭＯＸ工艺成功研制出多晶硅栅器件,其中Ｎ＋栅ＮＭＯＳ管的阈值电压为０．４５Ｖ,Ｐ＋栅ＰＭＯＳ管的阈值电压为－０．２２Ｖ,在１Ｖ和５Ｖ电源电压下多晶硅栅环振电路的单级门延迟时间分别为１．７ｎｓ和３５０ｐｓ,双多晶硅栅ＳＯＩ技术将是低压集成电路的一种较好选择。     

梁式引线GaAs混频二极管对

文中报导的砷化镓梁式引线反向并联二极管对,可应用于鉴相器、谐波混频器等宽带部件。该器件以半绝缘ＧａＡｓ为衬底,选择ＮｂＭｏ／ＧａＡｓ微合金形成肖特基势垒,ＳｉＯ２和聚酰亚胺双介质作为钝化保护膜,以及合理的工艺途径。器件抗烧毁能力强,可靠性好。其伏安特性ｎ因子小于１．１,结电容２Ｃｊ＝０．１～０．２ｐＦ,正向微分电阻为３～６Ω,分布电容较小,结电容差为ΔＣｊ≤０．０２５ｐＦ,正向电压差为ΔＶＦ≤２５ｍＶ。将该器件应用于１８～４０ＧＨｚ宽带分谐波混频器中,中频带宽为４～８ＧＨｚ,混频器的变频损耗低于２０ｄＢ,本振功率为１３ｄＢｍ。     

用于亚微米CMOS的轻掺杂漏工艺

本文研究了轻掺杂漏工艺对器件特性的影响。优化了轻掺杂区离子注入的剂量和能量。优化的ＳｉＯ２侧墙ＬＤＤ工艺有效地抑制了短沟道效应。研制成功了沟道长度为０．５μｍ的ＣＭＯＳ２７级环振电路，门延迟为１７０ｎｓ．     

双固相外延技术及高性能1μmCMOS／SOS器件的研究

本文较为详细地介绍了能有效地改善ＳＯＳ材料结晶质量的双固相外延ＤＳＰＥ工艺，给出了优化的工艺条件．通过比较用ＤＳＰＥ及普通ＳＯＳ材料制作的ＣＭＯＳ／ＳＯＳ器件和电路的特性可以看出，采用ＤＳＰＥ工艺能显著改善ＳＯＳ材料的表面结晶质量，应用ＤＳＰＥ工艺在硅层厚度为３５０ｎｍ的ＳＯＳ材料上成功地研制出了沟道长度为１μｍ的高性能ＣＭＯＳ／ＳＯＳ器件和电路，其巾ＮＭＯＳＦＥＴ及ＰＭＯＳＦＥＴ的泄漏电流分别为２．５ｐＡ和１．５ｐＡ，１９级ＣＭＯＳ／ＳＯＳ环形振荡器的单级门延迟时间为３２０ｐｓ．     

高性能BiCMOS制造技术及I/O电路优化

本文报导一套先进的ＢｉＣＭＯＳ集成电路制造技术，建立在ＣＭＯＳ工艺基础上的ＢｉＣＭＯＳ制造工艺，增加了双埋层，２．５微米本征外延层，双阱，基区，多晶硅发射区，深集电区和平坦化双层金属布线等工艺技术。器件性能测试和扫描电镜检查结果表明，双极器件和ＭＯＳ器件性能优良，ＢｉＣＭＯＳ器件的抗锁定性能比ＣＭＯＳ器件提高了一个数量级。     

在1．8GHz频率下功率密度为2．8W／mm的4H－SiCMESFET

本文论述了使用４Ｈ－ＳｉＣ衬底及外延层制作ＭＥＳＦＥＴ的方法，测得了栅长为０．７μｍ、栅宽为３３２μｍ的ＭＥＳＦＥＴ的直流、Ｓ参数和输出功率特性。当Ｖｄｓ＝２５Ｖ时，电流密度约为３００ｍＡ／ｍｍ，最大跨导在３８～４２ｍＳ／ｍｍ之间；当频率为５ＧＨｚ时，该器件的增益为９．３ｄＢ，ｆｍａｘ＝１２．９ＧＨｚ。当Ｖｄｓ＝５４Ｖ时，功率密度为２．８Ｗ／ｍｍ，功率附加效率为１２．７％。     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极的速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主。因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ技术显得愈发相似。本文例举了０．８μｍ和０．５μｍ的技术论点，ＢｉＣＭＯＳ电路与ＣＭＯＳ相比，成本稍有增加，但其性能提高一倍。     

自对准外延CoSi_2源漏接触CMOS器件技术

ＣＯ／Ｔｉ／Ｓｉ或ＴｉＮ／Ｃｏ／Ｔｉ／Ｓｉ多层薄膜结构通过多步退火技术在Ｓｉ单晶衬底上外延生长ＣｏＳｉ２薄膜，ＡＥＳ、ＲＢＳ测试显示ＣｏＳｉ２薄膜具有良好均匀性和单晶性．这种硅化物新技术已用于ＣＭＯＳ器件工艺．采用等离子体增强化学汽相淀积（ＰＥＣＶＤ）技术淀积氮氧化硅薄膜，并用反应离子刻蚀（ＲＩＥ）技术形成多晶硅栅边墙．固相外延ＣｏＳｉ２薄膜技术和边墙工艺相结合，经过选择腐蚀，可以分别在源漏区和栅区形成单晶ＣｏＳｉ２和多晶ＣｏＳｉ２薄膜，构成新型自对准硅化物（ＳＡＬＩＣＩＤＥ）器件结构．在Ｎ阱ＣＭＯＳ工艺     

亚微米BiCMOS工艺技术

ＢｉＣＭＯＳ是双极速度和驱动能力与ＣＭＯＳ的高密度和低功耗的结合。考虑到功耗原因，ＢｉＣＭＯＳ器件主要以ＣＭＯＳ为主，因此，双极器件通常并入ＣＭＯＳ核心工艺流程。当器件尺寸减小时，双极和ＣＭＯＳ的技术显得愈发相似。本文列举了０．８μｍ和０．５μｍ的技术论点。ＢｉＣＯＳ电路与ＣＭＯＳ相比，成本稍高但其性能提高一倍。     

Improving hydrogenation efficiency of polycrystalline silicon thin film transistors by a new approach

In this paper, a new hydrogenation process of poly-Si thin film for the fabrication of poly-Si thin film transistors (TFTs) is proposed. In the new approach, the hydrogenation of TFTs is performed before deposition of contact metal. N-channel and p-channel poly-Si TFTs with various channel lengths and widths were fabricated with the new and conventional processes for comparison. The results verified that the efficiency of hydrogenation has been improved remarkably by the new process. The field-effect mobility of carriers, the on state current, threshold voltage and the on/off states current ratio have been greatly improved, and the trap state density has been reduced significantly.     

Fabrication of Poly—Si TFT by Al—induced Lateral Crystallization at Low Temperature

Using a new low-temperature process (<600 ℃), the poly-Si TFT was fabricated by metal-induced lateral crystallization (MILC). An ultrathin aluminum layer was deposited on a-Si film and selectively formed by photolithography. The films were then annealed at 560 ℃ to obtain laterally crystallized poly-Si film, which is used as the channel area of a TFT. The poly-Si TFT showed an on/off current ratio of higher than 1×10 6 at a drain voltage of 5 V. The electrical properties are much better than TFT fabricated by conventional crystallization at 600 ℃.     

Dependence of off-leakage current on channel film quality in poly-Si thin-film transistors and analysis using device simulation

The dependence of off-leakage current on channel film quality in poly-Si thin-film transistors has been analyzed using two-dimensional device simulation. It is found that the off-leakage current decreases as the intragrain trap density decreases for the low V_gs. This is because the Phonon-assisted tunneling with Poole-Frenkel effect is the dominant mechanism of the carrier generation and the generation rate of carrier pair decreases as the intragrain trap density decreases. On the other hand, the off-leakage current slightly increases as the intragrain trap density decreases for the high V_gs. This is because the band-to-band tunneling is the dominant mechanism and the influence of the intragrain trap density to the carrier conductance is larger than that to the generation rate.     

掺砷多晶硅特性研究

用ＬＰＣＶＤ方法生长了掺Ａｓ多晶Ｓｉ薄膜，通过能谱分析，扩展电阻测量，扫描电子显微镜观测，发现用ＬＰＣＶＤ方法生长的掺Ａｓ多晶Ｓｉ可获得极高的掺Ａｓ浓度，Ａｓ对衬底材料（ＳｉＯ２或多晶Ｓｉ）具有超常的低温快扩散特性，掺Ａｓ多晶Ｓｉ经高温退火，晶粒大小有反常的变化。利用这些特性可成功地解决ＬＰＣＶＤ法生长掺Ａｓ多晶Ｓｉ所遇到的生长速度愈来愈慢，Ａｓ浓度愈来愈高，难以生长较厚掺Ａｓ多晶Ｓｉ等问题。     

Charge sheet model of a polysilicon thin-film transistor

A simple analytical model for the current–voltage characteristics of a poly-Si thin-film transistor (TFT) using charge sheet analysis has been developed. An effective doping due to the presence of trap levels at grain boundaries and the effect of diffusion current is considered. The model also takes into account the charge sharing factor, necessary to explain the characteristics of a short channel device. The results so obtained for both long- and short-channel lengths were compared with the experimental data and good agreement was found. The transconductance and the drain conductance were also evaluated.     

3GHz硅双极型微波静态分频器的设计

本文报道了一种超高速ＥＣＬ静态二分频器；介绍了该分频器的核心器件─—ＮＰＮ晶体管的结构和实现该结构的有关先进工艺，包括深槽隔离、多晶硅发射极、钻硅化物和浅结薄基区等；使用这种多晶硅发射极晶体管，３ｐｍ特征尺寸设计的１９级环形振荡器的平均门延迟小于５０ｐｓ．讨论了提高分频器工作频率的一些有效方法并给出了３．２ＧＨｚ硅静态分频器的电路设计和版图设计．     

多晶硅有源矩阵液晶显示器

本文首先就用来制造有源矩阵液晶显示器的非晶硅和多晶硅材料作了性能比较,然后描述了多晶硅薄膜晶体管阵列的制造方法,以及在制造方法上取得的进展。     

A Capacitor Voltage Clamped Dual Half-Bridge Series-Resonant Inverter for Home Cooking Applications

An induction heating appliance used for cooking includes more than one inductor, each being controlled by a separate inverter system. The main aim of this paper is to control each coil separately at a different frequency and power output by using the same inverter system. A working coil of two parts has been designed practically and a computer simulation has been carried out, using practical coil parameters. Each part of the coil has been operated at a different frequency and power output, which allows the use of vessels of two different diameters while obtaining a high coupling factor for both conditions. This also increases the efficiency of the system and improves power quality. The proposed topology can be applied to induction hotplates made up of several inductors in which the power and frequency must be separately regulated.     

Poly-Si Thin Film Grown by Excimer Laser Crystallization and Its Ellipsometric Analysis

A novel approach of two-step laser crystallization for the growth of poly-Si thin film on glass substrate is investigated. Using this approach, we fabricated poly-Si thin film transistors with electron mobility of 103 cm2/V·s and on/off current ratio of 1×10~7.They are better than those of the poly-Si TFTs fabricated by conventional single-step excimer laser crystallization. We also analyzed the structure of the laser crystallized poly-Si thin film by spectroscopic ellipsometry, and proposed the models to simulate the poly-Si thin film and calculated the ellipsometric spectra. The calculated results are in good agreement with the measured results.     

Electrical simulation of the flicker in poly-Si TFT-LCD pixels for the large-area and high-quality TFT-LCD development and manufacturing

In this paper, we present a new flicker evaluation model through the electrical simulation of the optical flicker phenomena in different kinds of poly-Si TFT-LCD arrays for the development and manufacturing of large-area and high-quality TFT-LCDs. We applied our flicker evaluation model to three different types of TFTs; excimer laser annealed (ELA) poly-Si TFT, silicide mediated crystallization (SMC) poly-Si TFT, and counter-doped lateral body terminal (LBT) poly-Si TFT. We compared the flicker quantitatively for these three different TFT-LCDs on 40 in. UXGA scale. We identified three major factors causing the flicker such as charging time, kickback voltage and leakage current, analyzed their relative contributions to the flicker, and evaluated the values of the flicker in decibel (dB) for the three different TFT-LCD arrays. In addition, we show that the flicker is very sensitive to the low-level (minimum) gate voltage due to the large leakage current of the poly-Si TFT, and the low-level gate voltage should be chosen carefully to minimize the flicker.