A simple process to produce a high quality silicon surface prior toselective epitaxial growth

A simple and low-cost process was devised to eliminate etch damage resulting from oxide etching on the seed-hole surface prior to selective epitaxial growth (SEG) of silicon. The process consists of a low power C ₂F₆ RIE step which was performed right after the oxide etch step in the same etch reactor. The use of this step excluded the need of a conventional sacrificial oxide to remove damaged silicon regions and residual polymers. The n-p diodes resulting from n-type SEG grown on p-type substrate were used to evaluate the quality of the silicon surface prior to SEG     

The pattern dependence of selectivity in low pressure selective epitaxial silicon growth

The dependence of selectivity on HC1 flow and operating pressure for an 850° C SiH₂Cl₂/ HC1 based SEG process has been investigated. The polysilicon nuclei density (#/cm² measured by optical microscope) on large unpatterned areas of deposited SiO₂ was used to quantify the selectivity of different process conditions. Three distinct selectivity regimes were identified: (a) a non-selective regime with >10⁶ nuclei/cm², (b) a pattern dependent regime with <10⁶ nuclei/cm², and (c) an intrinsically selective regime with <1 nuclei/cm². The intermediate, pattern dependent, selectivity regime was characterized by a much lower density of silicon nuclei in and around patterned areas where windows of Si are exposed, thus making a loss of selectivity more difficult to detect. This phenomenon is shown to arise from feature scale (<100 micron) lateral fluxes of gas phase species. An intrinsically selective regime suitable for VLSI manufacturing, which avoids the high nuclei density associated with the pattern dependent regime, is identified.     

Quasi-dielectrically isolated bipolar junction transistor withsubcollector fabricated using silicon selective epitaxy

A novel quasi-dielectrically isolated bipolar junction transistor (QDI-BJT) was developed for intelligent power ICs. Using a combination of junction and dielectric isolation, the QDI-BJT was achieved by selective epitaxial growth (SEG) of single-crystal silicon in an oxide-lined trench. Buried collectors formed by ion implantation and in situ doped SEG silicon drastically reduce collector resistance with no detrimental effects on transistor performance. The emitter-base and collector-base ideality factors at 1.10 and 1.09, respectively, were very close to those of similar devices fabricated in the substrate in the same die, indicating excellent crystal quality of the SEG silicon. Due to the use of a trench structure to facilitate isolation and control the SEG thickness, the QDI process can be used for any application where the thickness and resistivity of the control and power areas are independently optimized     

Excimer Laser‐Assisted In Situ Phosphorus Doped Si(1‐x)Gex Epilayer Activation

This paper presents results from experiments on laser‐annealed SiGe‐selective epitaxial growth (LA‐SiGe‐SEG). The SiGe‐SEG technology is attractive for devices that require a low band gap and high mobility. However, it is difficult to make such devices because the SiGe and the highly doped region in the SiGe layer limit the thermal budget. This results in leakage and transient enhanced diffusion. To solve these problems, we grew in situ doped SiGe SEG film and annealed it on an XMR5121 high power XeCl excimer laser system. We successfully demonstrated this LA‐SiGe‐SEG technique with highly doped Ge and an ultra shallow junction on p‐type Si (100). Analyzing the doping profiles of phosphorus, Ge compositions, surface morphology, and electric characteristics, we confirmed that the LA‐SiGe‐SEG technology is suitable for fabricating high‐speed, low‐power devices.     

A polysilicon contacted subcollector BJT for a three-dimensionalBiCMOS process

A polysilicon contacted subcollector (PCS) bipolar junction transistor (BJT) was fabricated using selective epitaxial growth (SEG) of silicon to form the active region. The fabrication is the first step in the development of a novel 3-D BiCMOS process. To study the efficacy of the polysilicon collector contact, three types of BJTs were fabricated and their collector resistances were compared. These were the PCS BJT, a BJT fabricated in SEG silicon grown from a shallow trench incorporating a shallow collector contact with a buried layer, and a BJT fabricated in the silicon substrate with a shallow collector contact but no buried layer. The PCS BJT exhibited the smallest collector resistance as well as excellent device characteristics, demonstrating its viability for a 3-D BiCMOS process     

Study of CVD nanowire high-k metal interface quality for interconnect level MOS devices

We report a study of low temperature gate stack on silicon nanowires compatible with Back-End-Of-Line (BEOL) integration. The same gate stack is deposited at low temperature on Si nanowires obtained thanks to either Chemical Vapor Deposition (CVD) or Selective Epitaxial Growth (SEG) in patterns. Gate stack characterization on CVD nanowires (NWs) shows low leakages and good agreement with simulated curves without interface states. A dramatic decrease of the capacitance in accumulation region and faster electron generation are observed and attributed to NW defects. In contrast, SEG devices reveals lower capacitance decrease with frequency but higher interface state density of about 10¹³ cm⁻².     

Elimination of the sidewall defects in selective epitaxial growth(SEG) of silicon for a dielectric isolation technology

Selective epitaxial growth (SEG) of silicon has not had widespread use as a dielectric isolation technology due to the near sidewall defects at the SiO₂/Si interface. These defects are located in the first 1-2 μm of the SEG/sidewall SiO₂ interface. Diode junctions intersecting the sidewall and 5 μm removed from the sidewall were fabricated in SEG material using thermally grown silicon dioxide (OX) and thermally nitrided thermal silicon dioxide (NOX) as the field insulating mask. Averaged over 16 devices of each type, diodes fabricated with NOX had much better low current I-V characteristics and minimum ideality factors (1.03) than diodes fabricated with OX field oxides (1.23). Junctions intersecting the NOX field insulator had nearly identical characteristics to bulk SEG     

A high-performance five-channel NMOSFET using selective epitaxialgrowth and lateral solid phase epitaxy

In this letter, a novel five-channel NMOSFET (FC-NMOS) using selective epitaxial growth (SEG) and lateral solid phase epitaxy (LSPE) is reported. The FC-NMOS is an integration of a conventional bulk NMOS, two vertical NMOS, and a gate-all-around NMOS. The top silicon layer for implementing the gate-all-around structure is obtained by using the LSPE with the SEG pillar as the silicon seed. The FC-NMOS has a 3.6× higher current drive as compared to the conventional bulk NMOS. This makes the FC-NMOS very promising for VLSI/ULSI applications     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

Degradation of insulators in Silicon Selective Epitaxial Growth(SEG) ambient

The degradation of various insulators in Silicon Selective Epitaxial Growth (SEG) ambient was studied. The insulators studied were thermal oxide, reoxidized nitride/oxide stack, poly-oxide, and nitrided oxide. Breakdown electric fields of MIS capacitors were measured and yields were calculated before and after the insulators were exposed to Silicon SEG ambient. It was found that the nitrided oxide was more resistant to degradation in the SEG ambient than thermal and poly oxide; results reported here for the first time. The increased resistance of nitrided oxide in SEG ambient coupled with their superior performance as thin gate insulators makes them an excellent candidate for use in novel 3-D structures using selective silicon growth     

Synthesis and Patterning of Prussian Blue Nanostructures on Silicon Wafer via Galvanic Displacement Reaction

Nanoscale materials directly interfacing semiconductors is a new area of nanoscience and nanotechnology. Tremendous attention has been paid to inorganic nano size crystals in recent years because of their significant properties. Prussian blue (PB) and its analogues could play important roles in the field of molecule‐based magnets, electrochromic materials, ion selectivity electrodes and biosensors. In this study, we report on fabricating Prussian blue patterns on silicon surface by combining the photolithographic techniques and galvanic displacement reaction, and the resulting patterns were characterized by scanning electron microscopy (SEM) and scanning electrochemical microscopy (SECM) on the basis of detection of catalytic current for the oxidation of H₂O₂.     

Three dimensional devices fabricated by silicon epitaxial lateral overgrowth

Selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon over oxide are used for novel device technologies in CMOS and bipolar with a large potential for BICMOS. A stacked inverted P-MOS device in crystalline Si on top of an oxidized poly-gate was fabricated with the critical “as-grown” interface state densities, between the ELO silicon grown over the existing poly-oxide, measured to be less than 2 × 10¹¹/ (cm²-eV) near midgap. A SiH₂Cl₂-HCl-H₂ in a LPCVD epitaxial system was employed at 150 Torr and at 900° C to produce the ELO/SEG material. The initial stacked-inverted 3D P-MOS devices typically show hole mobilities of greater than 160 cm²/V-s with adequate subthreshold characteristics for 3-dimensional CMOS implementation. A new form of SEG was used to grow single crystal silicon horizontally between dielectric walls to form SOI material in thin slabs, called confined lateral selective epitaxial growth (CLSEG). BJT-SOI device structures with β_dc > 150 were fabricated in CLSEG silicon to demonstrate the device quality material and to show the 3D-SOI capability.     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

8% Efficient thin‐film polycrystalline‐silicon solar cells based on aluminum‐ induced crystallization and thermal CVD

A considerable cost reduction could be achieved in photovoltaics if efficient solar cells could be made from polycrystalline‐silicon (pc‐Si) thin films on inexpensive substrates. We recently showed promising solar cell results using pc‐Si layers obtained by aluminum‐induced crystallization (AIC) of amorphous silicon in combination with thermal chemical vapor deposition (CVD). To obtain highly efficient pc‐Si solar cells, however, the material quality has to be optimized and cell processes different from those applied for standard bulk‐Si solar cells have to be developed. In this work, we present the different process steps that we recently developed to enhance the efficiency of pc‐Si solar cells on alumina substrates made by AIC in combination with thermal CVD. Our present pc‐Si solar cell process yields cells in substrate configuration with efficiencies so far of up to 8·0%. Spin‐on oxides are used to smoothen the alumina substrate surface to enhance the electronic quality of the absorber layers. The cells have heterojunction emitters consisting of thin a‐Si layers that yield much higher V_oc values than classical diffused emitters. Base and emitter contacts are on top of the cell in interdigitated finger patterns, leading to fill factors above 70%. The front surface of the cells is plasma textured to increase the current density. Our present pc‐Si solar cell efficiency of 8% together with the fast progression that we have made over the last few years indicate the large potential of pc‐Si solar cells based on the AIC seed layer approach. Copyright © 2007 John Wiley & Sons, Ltd.     

Fabrication of nickel stamp with improved sidewall roughness for optical devices

We proposed the simple and attractive fabrication method of nickel stamp with improved sidewall roughness for polymeric optical devices. For this, the imprinted optical devices patterns under optimum imprinting conditions were annealed to improve the sidewall roughness generated by the DRIE process in the silicon stamp fabrication. The annealed sidewall roughness is reduced to 24.6 nm, nearly decreasing by 76% compared with the result before the annealing. Then, low cost and durable nickel stamp with improved sidewall roughness was fabricated by the annealed polymeric patterns being used as original master for electroforming process. And, we verified the superiority of the improved nickel stamp by comparing the optical propagation losses for optical waveguides to be fabricated, respectively, using the nickel stamp and original silicon stamp. The optical waveguides fabricated by the imprint lithography using the improved nickel stamp was demonstrated that their optical losses were reduced as 0.21 dB/cm, which was less than the propagation loss for polymeric waveguides using the conventional original silicon stamp. This result could show the effectiveness of the fabricated nickel stamp with improved sidewall roughness. Furthermore, we were able to successfully fabricate a polymeric 1 × 8 beam splitter device using the improved nickel stamp. And, the insertion loss for eight channels obtained to be from 10.02 dB to 10.91 dB.     

Selective deposition of diamond films

Polycrystalline diamond films have been selectively deposited on a silicon surface. A novel process was developed which exposes a patterned, scratch damaged silicon area, surrounded by SiO₂, to a high pressure microwave plasma of hydrogen containing methane. The hydrogen plasma dissociates the methane injected into the reaction chamber, resulting in diamond deposition, which occurs only on the exposed silicon. Under the process conditions described in this work, some in situ plasma etching of the oxide is observed, resulting in little or no growth of diamond in unwanted areas, and further enhancing the selectivity. A variety of patterns and structures have been fabricated. Raman spectroscopy confirmed the films were diamond.     

Controlled Microfabrication of High‐Aspect‐Ratio Structures in Silicon at the Highest Etching Rates: The Role of H2O2 in the Anodic Dissolution of Silicon in Acidic Electrolytes

In this work the authors report on the controlled electrochemical etching of high‐aspect‐ratio (from 5 to 100) structures in silicon at the highest etching rates (from 3 to 10 µm min^?1) at room temperature. This allows silicon microfabrication entering a previously unattainable region where etching of high‐aspect‐ratio structures (beyond 10) at high etching rate (over 3 µm min^?1) was prohibited for both commercial and research technologies. Addition of an oxidant, namely H₂O₂, to a standard aqueous hydrofluoric (HF) acid electrolyte is used to dramatically change the stoichiometry of the silicon dissolution process under anodic biasing without loss of etching control accuracy at the higher depths (up to 200 µm). The authors show that the presence of H₂O₂ reduces the valence of the dissolution process to 1, thus rendering the electrochemical etching more effective, and catalyzes the etching rate by opening a more efficient path for silicon dissolution with respect to the well‐known Gerischer mechanism, thus increasing the etching speed at both shorter and higher depths.     

Effective Silicon Oxide Formation on Silica‐on‐Silicon Platforms for Optical Hybrid Integration

This paper describes an effective method for forming silicon oxide on silica‐on‐silicon platforms, which results in excellent characteristics for hybrid integration. Among the many processes involved in fabricating silica‐on‐silicon platforms with planar lightwave circuits (PLCs), the process for forming silicon oxide on an etched silicon substrate is very important for obtaining transparent silica film because it determines the compatibility at the interface between the silicon and the silica film. To investigate the effects of the formation process of the silicon oxide on the characteristics of the silica PLC platform, we compared two silicon oxide formation processes: thermal oxidation and plasma‐enhanced chemical vapor deposition (PECVD). Thermal oxidation in fabricating silica platforms generates defects and a cristobalite crystal phase, which results in deterioration of the optical waveguide characteristics. On the other hand, a silica platform with the silicon oxide layer deposited by PECVD has a transparent planar optical waveguide because the crystal growth of the silica has been suppressed. We confirm that the PECVD method is an effective process for silicon oxide formation for a silica platform with excellent characteristics.     

H2对UHV/CVD低温选择性外延生长Si1-xGex的影响

利用超高真空化学气相沉积(UHV/CVD)成功实现了Si_1-xGe_x的低温选择性外延生长,并研究了H2对选择性外延生长的影响及其作用机理. 以SiH4和GeH4为反应气源,在开有6mm×6mm窗口氧化硅片上进行Si_1-xGe_x外延层的生长.首先分别以不含H2(纯GeH4)和含H2(90% H2稀释的GeH4)的两种Ge源进行选择性外延生长.通过SEM观察两种情况下氧化硅片表面,发现H2的存在对选择性外延生长有至关重要的作用.接着以90% H2稀释的GeH4为Ge源,变化Si源和Ge源的流量比改变H2分压,以获得SiH4和GeH4 (90% H2）的最佳流量比，使外延生长的选择性达到最好. 利用SEM观察在不同流量比时，经40min外延生长后各样品的表面形貌，并对其进行比较，分析了H2分压在Si_1-xGe_x选择性外延生长中的作用机理.     

8英寸薄层硅外延片的均匀性控制方法

8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一.研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3％的前提下,外延层厚度和电阻率形成中间低、边缘略高的“碗状”分布可有效提高晶圆的良率水平.通过调整生长温度和氢气体积流量可实现外延层厚度的“碗状”分布,但调整温区幅度不得超过滑移线的温度门槛值.通过提高边缘温度来提高边缘10 mm和6 mm的电阻率,同时提高生长速率以提高边缘3 mm的电阻率,获得外延层电阻率的“碗状”分布,8英寸薄层硅外延片的的边缘离散现象得到明显改善,产品良率也有由原来的94％提升至98.5％,进一步提升了8英寸薄层硅外延片产业化良率水平.