Switched capacitor analog modulo integrator for application in open loop Sigma-Delta modulators

We introduce the switched capacitor analog modulo integrator, which to our knowledge is a new circuit. We introduce the amplitude modulated open loop ΣΔ modulator (OLSDM), which is an analog modulo integrator followed by a quantizer and a modulo differentiator. The mathematical equivalence between low pass ΣΔ modulators and OLSDM is explained. Behavioral simulations confirm the equivalence. The necessary circuit, a switched capacitor analog modulo integrator, is explained in detail. Behavioral level simulations in SPICE of the analog modulo integrator verify the function, and prove the concept of amplitude modulated OLSDM.     

可控模拟延迟线的研究

本文提出了一种用我国首创的DYL集成线性与或门设计成的模拟延迟线。这种延迟线不仅具有电路结构简单、信号传递速度快等特点,而且电路的延迟量可以用数字量直接控制。     

Analog Hardware Implementation of Continuous-Time Adaptive Filter Structures

We have implemented a four-tap adaptive filter in a continuous-time analog VLSI circuit. Since an ideal delay is impossible to implement in continuous-time hardware, we implemented the delay line as a cascade of low-pass filters (called the gamma filter). Since many years of research in our lab has shown that the gamma filter outperforms the ideal delay line for a wide range of applications, the gamma filter should not be considered merely a crude approximation of the ideal delay line. We show measured results from an analog chip that solves the problem of system identification–identifying an unknown linear circuit from its input/output relationship. Furthermore, we believe that a cascade of all-pass filters (called the Laguerre filter) will potentially outperform the gamma. We have built an adaptive Laguerre filter and show that its measured convergence rate is superior to that of the gamma. Finally, rather than perform gradient descent on a multimodal error function to determine a single optimal time constant, we propose multi-scale realizations of these delay line structures.     

Aspects of the current understanding of the supercurrent transport in (Bi,Pb)2Sr2Ca2Cu3O10 silver-sheathed Tapes—the “railway-switch” model

The “railway-switch” model describes the superconducting current transport in (Bi,Pb)₂Sr₂Ca₂Cu₃O₁₀ silver-sheathed tapes under the basic assumption that small-angle c axis tilt grain boundaries (“railway-switch”) constitute strong intergrain links for the supercurrent in the textured filament [B. Hensel, J.-C. Grivel, A. Jeremie, A. Perin, A. Pollini, and R. Flükiger,Physica C 205, 329 (1993)]. We give an overview of the model and some recent experimental results with the objective to identify the mechanisms that limit the critical current density. The measurements have been performed on monofilamentary “powderin-tube” samples [J_c(T < 77K, B < 0 T) < 20..30 kA/cm²] that were prepared in long lengths by rolling as the only tape-forming process. We conclude that the low intragrain critical current density j_c ^c along the c axis (or the even lower critical current density j_c ^t across twist boundaries or intergrowths) is the dominant limitation for the transport critical current in high-quality tapes. We discuss possible starting points for a performance improvement of the (Bi,Pb)₂Sr₂Ca₂Cu₃O₁₀ silver-sheathed tapes for applications. On leave from Consorzio INFM, Universitá di Genova, Italy.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

Integrated Time-to-Digital Converters Based on Interpolation

The main features of two time-to-digital convertersbased on interpolation are presented, together with some measurementresults. The first converter is based on digital delay line interpolatorsand has been implemented in a 1.2 µm CMOS process.It has a single-shot resolution of 1 ns (-value)and a nonlinearity less than ±50 ps in the measurementrange 5 to 500 ns. The power consumption of the circuit is 15mW. The second time digitizer has analog interpolators basedon time-to-voltage conversion and has been implemented in a 1.2 µm BiCMOS process. It has a single-shot resolutionof 50 ps and a nonlinearity less than 150 ps in the measurementrange 1 to 300 ns. The power consumption of this circuit is 200mW.     

Giant traps on the surface of hydride vapor phase epitaxy-grown free-standing GaN

Extended defects on the top surface of a 250-μm-thick free-standing GaN sample, grown by hydride vapor phase epitaxy (HVPE), were studied by deep level transient spectroscopy (DLTS) and scanning surface potential microscopy (SSPM). For comparison, similar studies were carried out on as-grown HVPE-GaN samples. In addition to the commonly observed traps in as-grown HVPE-GaN, the DLTS measurements on free-standing GaN reveal a very high concentration of deep traps (∼1.0 eV) within about 300 nm of the surface. These traps show nonexponential capture kinetics, reminiscent of those associated with large defects, that can accumulate multiple charges. The SSPM measurements clearly reveal the presence of charged microcracks on the top surface of the sample. It appears that the “giant traps” may be associated with these microcracks, but we cannot rule out the involvement of other extended defects associated with the near-surface damage caused by the polishing/etching procedure.     

Atomic structure ofDX centers: Theory

A structural model forDX centers in Al _x Ga_1-x As alloys which explains their unusual properties in terms of two distinct bonding configurations for donor impurities is proposed. The results of ourab initio self-consistent pseudopotential calculations showDX to be a “negative-U” defect center. It results from a large lattice relaxation which is different for a Group IV than a Group VI donor. The proposed structural model provides a satisfactory explanation of the properties ofDX centers.     

基于空间特征的非线性电路神经网络诊断

本文提出线性模拟电路的单、双、三故障空间特征,采用分段线性模型（PWL）将非线性电路线性化,通过遗传算法求电路的容羞范围,用神经网络对非线性嘲络进行诊断。本文的方法大火减少了模拟计算量,同时,使神经网络的训练过程加快,训练误差减少,并大大提高了诊断的正确率。     

An Analog Delay Circuit for On-Line Visual Confirmation of Discriminated Neuroelectric Signals

An analog delay circuit which utilizes an inexpensive commercially available analog shift register is described. The delay circuit when used in conjunction with a window discriminator will display "on-line" visual confirmation of single neural events from extracellular recordings containing more than one spike class. The delay can be changed to include the entire spike waveform by adjusting a potentiometer in the delay circuit.     

AN ANTI-ALIASING FILTER FOR ∑△ ADC

An anti-aliasing filter for ΣΔ ADCs using a combination of active RC and analog FIR filters is presented in this letter. The first order active RC filter is set at 100kHz to minimize the die size and variations of linear phase and gain in 0–4kHz passband. The 2-tap FIR filter provides more than −53dB attenuation at 2MHz ±4kHz frequency range. The proposed filter achieved more than −76dB attenuation at sampling frequency with ±0.01° phase linearity and ±0.02dB gain variation within 0–4kHz bandwidth. The active die area of the fully differential filter is 0.17mm² in 0.5μm CMOS technology. The experimental and simulation results have been obtained and the feasibility of the proposed method is shown. Supported by Foundation for University Key Teacher by the Ministry of Education of China     

Practical considerations for analog operation of bucket-brigade circuits

The bucket-brigade circuit offers a means of implementing a clock-controlled analog delay line in monolithic form. Operating in the sampled-data domain, it combines some of the advantages of both analog and digital circuits and appears to have a strong application potential in analog signal processing systems. In this paper, the analog operation of bucket-brigade circuits is described with respect to such practical operating considerations as bandwidth, dynamic range, linearity, power dissipation, baseband, signal recovery, a clock waveform noise. Experimental results from p-channel MOSFET and n-channel JFET brigades are presented.     

一种灵活多用的抽头模拟延迟线

介绍了一种灵活多用的３２抽头模拟延迟线ＢＡＤ３２，分析了它的工作原理和应用中必须注意的几个问题，给出了几个典型应用实例。     

SnSe single crystals: Sublimation growth,deviation from stoichiometry and electrical properties

Large SnSe single crystals of high metallurgical quality have been grown by a closed tube vapor phase technique. Hall measurements on annealed and quenched samples were performed to establish the stability range of the compound. The crystals are p-type with hole concentrations between 3 × 10¹⁵ and 2 × 10¹⁸ cm⁻³ and mobilities up to 7 × 10³ cm /Vs at 77 K.     

一种大间距短波线列红外探测器用读出电路的设计

介绍了一款大间距双波段短波线列红外探测器用读出电路的设计详情,电路采用CTIA输入方式,模拟通道采用11级TDI进行信号的时间延迟累加平均。文章主要介绍了电路输入级、列级信号处理电路的设计及仿真分析,给出了全电路的整体仿真结果,并在文章最后介绍了电路实际测试结果。     

“BLOCK”: An experimental expert system for the design of circuits

This paper presents an experimental expert system named as “BLOCK” for the design of analog circuits, in order to seek ways to result in a circuit expert system with high-level. With the given requirements of both output and input signals fed to the circuit, the “BLOCK” system is able to produce the block design of the circuit by itself rapidly instead of by circuit designers in the ordinary way.     

A 1.2.1 post-filter for color-difference interpolation of a MACvideo signal

The design and implementation of a digital video application-specific integrated circuit (ASIC) that performs the line interpolation of the missing color samples of a digitized multiplex analog component (MAC) video signal are described. The main part of this circuit is a specific 864×8-bit memory designed as a double-chroma digital delay line. The design is based on 2-μm double-metal N -well CMOS technology. The chip area is 35.6 mm² and it operates with a clock rate of 13.5 MHz. This circuit, which also performs phasing and blanking of the 8-bit digitized luminance and chrominance samples, is a part of a digital decoder used for the reception of video TV signals coded according to the MAC family system     

Computer-aided analysis of solid-state analog delay lines using conventional circuit analysis programs

A method is described for analyzing the two-dimensional behavior of minority carriers in a solid-state analog delay line by applying, without modification, existing computer-aided circuit analysis programs to a lumped model. Development of the model in two dimensions is based on an approximate solution of the minority carrier partial differential equation using an analogous electrical network. The model includes injecting and collecting junction nonlinearities and thereby permits the study of responses to arbitrary external excitations. Several examples of the use of the model are given.     

Comment on “realization of series and parallel R-L and C-D impedances using single differential voltage current conveyor”

The comment is related to the recently published paper given in [1] dealing with the implementation of series and parallel R-L and C-D impedances using a single differential voltage current conveyor (DVCC). Nevertheless, straightforward analysis of the circuit in Fig. 3(b) of [1] and also given in Fig. 1 shows that it has a problem because it makes its input voltage V _in = 0. Therefore, it can not realize parallel (–L)–(–R) simulator as claimed in [1]. Alternatively, a circuit given in Fig. 2 for realizing parallel (–L)–(–R) simulator employing a single minus-type DVCC (DVCC–) and a minimum number of passive components is proposed. The introduced circuit employs a grounded capacitor, and requires no critical component matching constraints thus it is suitable for fully integrated circuit technology. If plus-type DVCC (DVCC+) is replaced instead of the DVCC–, this proposed simulator can realize parallel (L)–(R) simulator. Fig. 1 The circuit proposed in Fig. 3(b) of [1]

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Fig. 2 Presented circuit for realizing parallel (+L)–(+R) and parallel (L)–(R) simulators depending on the type of the DVCC

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一种高精度大动态范围的距离模拟脉冲发生方法研究

现有的产生距离模拟脉冲的方法中,数字延时电路只能达到ns量级的精度,模拟延时电路的延时范围又不足够作为距离模拟脉冲的使用,为了实现高精度大动态范围的延时,来产生激光测距仪的距离模拟脉冲,在研究了现有方法的基础上,采用了数模结合的方案,设计了一种同时满足高精度和大动态范围的延时脉冲信号发生电路,并对其精度和重复性进行了测试,可以实现2 s～4 ms 的延时范围并具有0.1 ns的延时精度,即可以模拟300 m～600 km的距离并具有 1.5 cm的距离精度。解决了现有的距离模拟电路无法同时满足高精度、大动态范围的矛盾。