基于线扫描的VLSI版图几何验证核心算法的固化

ＶＬＳＩ集成度的飞速提高使设计过程复杂化，也对版图验证工具的处理能力与性能提出更高的要求。将版图验证的核心算法固化在专用硬件上，是一类非常有效的方法。本文提出了一种在版图验证算法中得到广泛运用的线扫描算法的硬件实现方法，利用有限状态机和流水线结构兼顾算法的顺序性和硬件的并行度，并通过近似的直接处理ＰＣＩ／Ｏ数据流提高处理大批量数据的能力。系统以一块ＰＣ接口板的形式实现。测试结果表明了约５０倍的加速比。     

基于线扫描的VLSI版图几何验核心算法的固化

ＶＬＳＩ集成度的飞速提高使设计过程复杂化，也对版图验试工具的处理能力与能力提出了更高的要求。将版图验证的核心算法固化在专用硬件上，是一类非常有效的方法。     

二进制堆排序算法的改进研究

基于对网络服务质量中队列调度算法的介绍和分析,从队列的优先级角度出发,对经典的二进制堆Heap调度排序算法进行了改进,提出了一种新的Heap＋算法,该算法充分利用原算法出队、入队操作数固定的特点,使其在保证硬件实现复杂度低的情况下能够做到出队、入队操作的流水化,从而达到高度的并行性。且具备很高的资源利用率和可扩展性,可用于高速链路上高精度虚拟时间的排序操作。     

嵌入式单精度扩展浮点RISC微处理器的设计

文章介绍了一种单精度浮点RISC微处理器的核心设计思想，改进设计了一种新颖的芯片内置总线仲裁器控制总线、中断处理机管理中断、数据中继器操作存储器。采用三阶布斯算法和浮点并行算法设计FALU和FMUL，并设计了嵌入式128KSRAM，最后用UMC0．25μmCMOS工艺库进行综合、布局布线完成版图设计。版图后模拟验证以及CPLD硬件仿真验证表明：微处理器工作主频达到50MHz，全部共88条指令运行正常。     

船用雷达复杂算法的FPGA实现

随着芯片技术的迅猛发展，越来越多的技术被应用到硬件数字处理领域。在硬件设计中也越来越多地使用了更为复杂的算法。但是，由于硬件设计本身的原因，用其实现复杂算法始终略感欠缺。目前在复杂算法的硬件实现上，主要有两种方式：一是以运算能力见长的、以指令方式运行的DSP处理器；二是以并行处理和可编程的FPGA为主的ASIC设计；两种方式各有所长。文中主要是针对在设计船用雷达信息处理系统中所涉及到的一些较为复杂算法，如跟踪算法、堆栈排序和数据存储等，谋求以FPGA方式的较优实现。通过实现设计中用到的复杂算法，提出硬件实现复杂算法的一些优化方法，以及可供利用的诸如Matlab的Simulink模块库中Xilinx组件等的工具软件。     

一种实现TCAM快速增量更新的算法

三重内容可寻址存储器TCAM（ternary content-addressable memory）是执行快速路由查找的常用硬件设备。在TCAM中进行最长前缀匹配操作最糟糕情况可能需要次存储操作，这里提出了一种算法来处理TCAM，结果使增量更新时间在最糟糕情况保持较小。通过对该算法与其他算法的性能分析，证明该算法在前缀长度排序限制条件下较常用算法更优。     

VLSI版图DRC验证算法的优化

介绍了版图验证的几种方法:扫描线算法和层次化验证算法,并比较其优缺点,最后着重介绍了层次式与扫描线综合验证算法,并在SUN工作站上用C 实现。     

实时嵌入式系统中高效定时器算法的实现

文章提出了一种实时嵌入式系统中高效定时器算法的实现手段：通过采用单循环队列定时器算法解决了在多队列计时算法中存在的冗余操作和排序操作的缺点。使定时器计时方法更有效率，更具有伸缩性，能适应不同规模的嵌入式系统。     

一种基于后缀排序快速实现Burrows-Wheeler变换的方法

近年来,Bzip2压缩算法凭借其在压缩率方面的优势,得到了越来越多的应用,Bzip2的核心算法是Burrows-Wheeler变换(BWT), BWT能有效的将数据中相同的字符聚集到一起,为进一步压缩创造条件。在硬件实现BWT时,常用的基于后缀排序的算法能有效克服BWT消耗存储资源大的问题,该文对基于后缀排序实现BWT的方法进行了详细分析,并且在此基础上提出了一种快速实现BWT的方法后缀段算法。仿真结果表明后缀段算法在处理速度上比传统的基于后缀排序的算法有很大的提高。     

基于FPGA的并行全比较排序算法

基于FPGA硬件技术,以空间换时间的思路,提出了一种并行全比较的排序算法。该算法通过对数据的并行全比较,计算出每个数据在排序中的位置实现数据排序。该算法可在4个时钟周期内实现数字序列的排序,通过实验证明,实时性好,通用性强。     

A highly reliable mask inspection system

An automatic system for inspecting micro mask defects with 1-µm minimum detectable size has been developed. An outline of the system is as follows: The pattern image obtained with a pickup tube is converted into binary video signals which are transferred into two parallel logic circuits for detecting pattern defects. One is based on the pattern-analyzing method, for which one of four algorithms for detecting micro defects is presented in detail. The other is based on the design-pattern data-comparing method, where the data compression scheme and a new idea for avoiding mask alignment errors are adopted. A software system outline, very important in assisting the hardware functions in this system, is also presented. The results of experiments for determining system performance indicate that the system can detect ≥1-µm diameter defects or loss patterns with high probability by complimentary use of the two methods. A 4-in by 4-in mask can be inspected within 100 rain.     

随机间距稀疏三元循环相位掩膜矩阵可压缩成像

可压缩成像是一种新兴的基于压缩感知理论的新成像技术,其核心思想是如果空间场景是稀疏或可压缩,那么它可以用远少于经典的Nyquist采样数目的测量值捕获的足够信息重构原场景;构建合适的测量矩阵并易于使用物理实现压缩感知理论中对于图像的随机线性测量是可压缩成像理论实用化的关键之一。该文在研究Bernoulli和Circulant矩阵的基础上,提出一种新的随机间距稀疏三元循环相位掩膜矩阵。模拟实验结果表明,在可压缩双透镜成像系统单次曝光下,与Bernoulli和Bernoulli-Circulant相位掩膜矩阵相比,新相位掩膜矩阵的成像信噪比与之相当;但是该文提出的矩阵随机独立变元个数和非零元个数显著减少,易于数据存储与传输;更重要的是物理上更容易实现,重构时间是只有原来的约20%~50%。新的相位掩膜矩阵的研究对于可压缩成像理论的实际应用具有重要的意义。     

一种新颖的UWB成形脉冲算法

超宽带（UWB）通信系统利用优化成形脉冲方法，可以产生符合美国联邦通信委员会（FCC）制订的辐射限值的发射信号。此方法在数学表达上简单、清晰。仿真结果表明，该方法可以使UWB成形脉冲的功率谱在高、低频带都能逼近FCC的标准辐射值，得到的组合系数表达简单。在硬件实现时能够减少寄存器数量和提高运算速度。     

Single event upset mitigation by means of a sequential circuit state freeze

This paper describes a novel design technique for hardening sequential circuits against Single Event Transients (SETs) and Single Event Upsets (SEUs) in non-volatile FPGAs. Double Modular Redundancy (DMR) is used to detect the presence of a SET in a sequential circuit. However, DMR solutions are only able to detect SET’s and not mask or correct them. Therefore, extra functionality is required to mask and correct the error after it has been detected. The central idea of the method proposed is to “freeze” the sequential circuit at a particular state when a SET is detected. As soon as the SET dissipates, the circuit is “unfrozen” so that it can continue with normal operation. Due to the short SET lifetime versus much longer circuit clock periods, the “frozen” state will normally not last more than one clock period. The proposed scheme is suitable for delay-insensitive applications requiring minimal hardware overhead.The proposed DMR method is thoroughly tested on ITC99 benchmarks. With a small delay of one clock period whenever a SET is detected, the proposed method offers immunity against the errors caused by SETs in non-volatile FPGA systems.     

Built-in test of CMOS state machines with realistic faults: asystem perspective

The design of built-in test systems for large arrays is approached from the viewpoint of detecting real faults in the mask layers of a typical CMOS process. The resulting testable design and built-in test system provides a practical compromise between the costly hardware augmentation plaguing existing techniques and circuit independence of the test procedure. Built-in testability is achieved independently of feedback. Therefore, combinational and sequential circuits can be tested in parallel with exactly the same hardware and method. The test-specific hardware overhead decreases rapidly with increasing circuit size and falls below 10% for large arrays with more than 100 product terms. No additional gate delays are introduced into the critical path by the test circuitry. The normal circuit performance is, therefore, left intact with the exception of a minimal degradation associated with adding tristate capability to the input buffers     

卷积神经网络在目标检测中的应用及FPGA实现

针对传统目标检测算法在复杂背景条件下的对红外弱小移动目标的检测能力弱,虚警率高等问题,提出了一种基于卷积神经网络的目标检测方法,分析了卷积神经网络的结构、特点,将卷积神经网络应用到红外弱小目标检测领域,选择卷积神经网络模型,学习训练学习出合适的模型参数,并将算法在以FPGA为核心的硬件平台上进行移植。实验表明,本文的算法实时性好,硬件移植工作量小,在复杂背景下能够得到目标掩码信息、有效检出目标。     

SMPDP中荧光粉层制备方法的对比与研究

荫罩式等离子体显示器（SMPDP）是一种由金属荫罩板代替传统障壁的新型PDP。针对SMPDP结构的特殊性，讨论了丝网印刷法和喷涂法制备荧光粉层的制作工艺，并对比其优劣。实验结果表明：采用喷涂方法可以在SMPDP的荫罩孔内壁制备致密、均匀的荧光粉层，与掩膜配合使用，可在荫罩上制备三基色荧光粉，满足SMPDP实现彩色的需要。因此，喷涂方法是制备SMPDP三基色荧光粉层行之有效的最佳途径。     

PFM：一种抗高阶功耗攻击的SMS4算法

针对已有的SMS4功耗攻击方法,设计了一种适合低功耗小面积的固定值掩码SMS4算法.首先,对SMS4算法结构及内部加密运算流程进行研究;设计了一种SMS4原子掩码算法来抗高阶功耗攻击,该方法使各中间变量均被掩码;在此方法的基础上,为了减少芯片的面积和功耗以适应特殊环境下的加密应用(如特殊环境的传感器加密通信节点),提出了一种改进的固定值掩码算法:伪随机固定值掩码算法(PFM)及其实现技术.实验结果证明,该方法在芯片面积和功耗增加不大的情况下,可以有效抵抗二阶差分功耗攻击.     

Two-dimensional optical mask design and atom lithography

Atom lithography is one of the latest proposals for high-resolution printing. The mask design and generation is key step for implementation of this method. In this paper, we have theoretically investigated and proposed a new method for two-dimensional optical mask design in atom lithography. A new method for realization of our proposed technique based on guided modes will present. With our proposed idea one can easily print every kind of two-dimensional patterns. This method can lead us to produce the nano-scale electronic and optical devices and systems. Also, a suitable algorithm for mask generation is proposed.     

Efficient Masking Methods Appropriate for the Block Ciphers ARIA and AES

In this paper, we propose efficient masking methods for ARIA and AES. In general, a masked S‐box (MS) block can be constructed in different ways depending on the implementation platform, such as hardware and software. However, the other components of ARIA and AES have less impact on the implementation cost. We first propose an efficient masking structure by minimizing the number of mask corrections under the assumption that we have an MS block. Second, to make a secure and efficient MS block for ARIA and AES, we propose novel methods to solve the table size problem for the MS block in a software implementation and to reduce the cost of a masked inversion which is the main part of the MS block in the hardware implementation.