Single Event Transient acquisition and mapping for space device Characterization

It is necessary for space applications to evaluate the sensitivity of electronic devices to radiations. It was demonstrated that radiations can cause different types of effects to the devices and possibly damage them [1] [2]. The interest in the effect of Single Event Transient (SET) has recently risen because of the increased ability of parasitic signals to propagate through advanced circuit with gate lengths shorter than 0.65 nm and to reach memory elements (in this case they become Single Event Upset (SEUs)). Analog devices are especially susceptible to perturbations by such events which can induce severe consequences, from simple artifacts up to the permanent fail of the device. This kinds of phenomena are very difficult to detect and to acquire, because they are not periodical. Furthermore, they can vary a lot depending on different parameters such as device technology and biasing. The main obstacle for the analysis is due to the maximum frequency of these signals, which is unknown. It is consequently difficult to set a correct sample frequency for the acquisition system. In this document a methodology to evaluate SETs in analog devices is presented. This method allows to acquire automatically these events and to easily study the sensitivity of the device by analyzing a “SETs cartography”. The advantages are different: it allows to easily acquire and analyze the SETs in an automatic way; the obtained results allow the user to accurately characterize the device under test; and, finally, the costs due to the implementation of the tests are lower than a classical analysis performed by a particle accelerator.     

On the prediction of radiation-induced SETs in flash-based FPGAs

The present work proposes a methodology to predict radiation-induced Single Event Transient (SET) phenomena within the silicon structure of Flash-based FPGA devices. The method is based on a MonteCarlo analysis, which allows to calculate the effective duration and amplitude of the SET once generated by the radiation strike. The method allows to effectively characterize the sensitivity of a circuit against the transient effect phenomenon. Experimental results provide a comparison between different radiation tests data, performed with different Linear Energy Transfer (LET) and the respective sensitiveness of SETs.     

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.     

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits

Recent radiation ground testing campaigns of digital designs have demonstrated that the probability for Single Event Transient (SET) propagation is increasing in advanced technologies. This paper presents a hierarchical reliability-aware synthesis framework to design combinational circuits at gate level with minimal area overhead. This framework starts by estimating the vulnerability of the circuit to SETs. This is done by modeling the SET propagation as a Satisfiability problem by utilizing Satisfiability Modulo Theories (SMTs). An all-solution SMT solver is adapted to estimate the soft error rate due to SETs. Different strategies to mitigate SETs are integrated in the proposed framework to selectively harden vulnerable nodes in the design. Both logical and temporal masking factors of the target circuit are improved to harden sensitive paths or sub-circuits, whose SET propagation probability is relatively high. This process is repeated until the desired soft error rate is achieved or a given area overhead constraint is met. The proposed framework was implemented on different combinational designs. The reliability of a circuit can be improved by 64% with less than 20% area overhead.     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.     

脉冲激光试验评估模拟电路单粒子效应

利用脉冲激光对典型模拟电路的单粒子效应进行了试验评估及加固技术试验验证,研究2种不同工艺的运算放大器的单粒子瞬态脉冲(SET)效应,在特定工作条件下两者SET脉冲特征规律及响应阈值分别为79.4 pJ和115.4 pJ,分析了SET脉冲产生和传播特征及对后续数字电路和电源模块系统电路的影响。针对SET效应对系统电路的危害性,设置了合理的滤波电路来完成系统电路级加固,并通过了相关故障注入试验验证,取得了较好的加固效果。     

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree

The soft error rate (SER) due to heavy-ion irradiation of a clock tree is investigated in this paper. A method for clock tree SER prediction is developed, which employs a dedicated soft error analysis tool to characterize the single-event transient (SET) sensitivities of clock inverters and other commercial tools to calculate the SER through fault-injection simulations. A test circuit including a flip-flop chain and clock tree in a 65 nm CMOS technology is developed through the automatic ASIC design flow. This circuit is analyzed with the developed method to calculate its clock tree SER. In addition, this circuit is implemented in a 65 nm test chip and irradiated by heavy ions to measure its SER resulting from the SETs in the clock tree. The experimental and calculation results of this case study present good correlation, which verifies the effectiveness of the developed method.     

Programmable single-electron transistor logic for future low-power intelligent LSI: proposal and room-temperature operation

This paper proposes, for the first time, the concept of programmable logic circuit realized with single-electron transistors (SETs). An SET having nonvolatile memory function is a key element for the programmable SET logic. The writing and erasing operations of the nonvolatile memory function make it possible to tune the phase of Coulomb oscillations. The half-period phase shift induced by the memory function makes the function of SETs complementary to that of the conventional SETs. As a result, SETs having nonvolatile memory function have the functionality of both the conventional (nMOS-like) SETs and the complementary (pMOS-like) SETs. By utilizing this fact, the function of SET circuits can be programmed with great flexibility, on the basis of the information stored by the memory functions. We have successfully fabricated SETs that operate at room temperature and observed the highest room-temperature peak-to-valley current ratio of Coulomb oscillations. The operation of the programmable SET logic is demonstrated using the room-temperature operating SETs. This is the first demonstration of room-temperature SET logic operation. The proposed programmable SET logic provides the potential for low-power, intelligent LSI chips suitable for mobile applications.     

硅基单电子晶体管的可控制备

采用电子束曝光、感应耦合等离子体刻蚀和热氧化等工艺技术,通过独特的图形反转设计,即在电子束曝光时采用负的曝光图形,并以电子束曝光的光刻胶作为掩膜进行干法刻蚀,通过后续的干法热氧化等工艺,在磷离子重掺杂的绝缘体上硅基底上成功地制备出单电子晶体管。该方法具有高精度、结构可控、可重复和加工成本低的优点,可作为一种批量制备单电子晶体管的工艺技术。所制备的单电子晶体管在2.6 K到100 K的温度范围内呈现出明显的库仑阻塞效应,导通电阻小于100 kΩ。该单电子晶体管将成为高速、高灵敏度射频电路的关键器件。     

Buffer单元单粒子效应及其若干影响因素研究

基于标准0.13μm工艺使用Sentaurus TCAD软件采用3D器件/电路混合模拟方式仿真了buffer单元的单粒子瞬态脉冲。通过改变重离子的入射条件,得到了一系列单粒子瞬态电流脉冲(SET)。分析了LET值、入射位置、电压偏置等重要因素对SET峰值和脉宽的影响。研究发现,混合模式仿真中的上拉补偿管将导致实际电路中SET脉冲的形状发生明显的变化。     

A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs

Flash-based Field Programmable Gate Array (FPGA) devices are nowadays golden core of many applications especially in space and avionic fields where reliability is an important concern. In particular, for Flash-based FPGAs, when adopted in those applications, the main concern is radiation-induced voltage glitches known as Single Event Transient (SET) in the combinational logic. In this work, a new CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect. This tool has been applied to EUCLID space mission project including more than ten modules. The experimental results demonstrate the efficiency of the proposed tool.     

Single Event crosstalk shielding for CMOS logic

With advances in technology scaling, CMOS circuits are increasingly more sensitive to transient pulses caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event transients, but in these designs, Single Event crosstalk effects have been ignored. In order to complement the Single Event upset (SEU) hardening process, coupling effects among interconnects need to be considered in the Single Event hardening and analysis of CMOS logic gates due to technology scaling effects that increase both SE vulnerability and crosstalk effects. As technologies advance, the coupling effects increasingly cause SE transients to contaminate electronically unrelated circuit paths which can in turn increase the “Single Event susceptibility” of CMOS circuits. Serious effects may occur if the affected line is a clock line or an input line of voters in triple-modular redundancy (TMR) circuit. Hence, this work first analyzes Single Event crosstalk on recent technologies and then proposes hardening techniques to reduce Single Event crosstalk. Hardening results are demonstrated using HSpice Simulations with interconnect and device parameters derived in 90 nm technology.     

Single event transient effects in a voltage reference

The Single Event Transient response of the LM236 band gap voltage reference from Texas Instruments is analyzed through heavy ion experiments and simulation. The LM236 circuit calibration was performed using generic transistor parameters that were subsequently optimized using device and circuit simulations. This technique avoids the requirement for performing detailed device-level parameter extraction and simplifies the SET methodology for circuit calibration.     

Silicon single-electron transistors with sidewall depletion gatesand their application to dynamic single-electron transistor logic

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology     

一种基于互补型单电子晶体管的全加器电路设计

基于单电子晶体管(SET)的I-V特性和CMOS数字电路的设计思想,提出了一种由28个互补型SKT构成的全加器电路结构。该全加器优点为：简化了“P—SET”逻辑块;通过选取一组参数使输入和输出高低电平都接近于0．02mV和0mV,电压兼容性好;延迟时间短,仅为0．24ns。SPICE宏模型仿真结果验证了它的正确性。     

混合SETMOS神经元分段线性输出函数的实现

提出了一种结构简单的神经元分段线性输出函数SETMOS实现方式。理论分析了恒流源偏置下单电子晶体管(SET)器件的特性和神经元分段线性输出函数。利用SET和金属氧化物场效应晶体管(MOSFET)混合结构实现了分段线性输出函数电路,并通过仿真分析得到了分段线性特性,提出了具体相应的调节方法,验证了该混合结构功能的正确性。结果表明,该混合电路具有结构简单,nm级特征尺寸,分段线性度好,静态功耗极低,约200nW,驱动负载工作能力强,输出电压可达几百毫伏,易于大规模神经网络电路的实现及应用和集成度的进一步提高。     

A Practical Approach to Single Event Transient Analysis for Highly Complex Design

Single Event Transients are considerably more difficult to model, simulate and analyze than the closely-related Single Event Upsets. The work environment may cause a myriad of distinctive transient pulses in various cell types that are used in widely different configurations. We present practical methods to help characterizing the standard cell library using dedicated tools and results from radiation testing. Furthermore, we analyze the SET propagation in logic networks using a standard (reference) serial fault simulation approach and an accelerated fault simulation technique, taking in account both logic and temporal considerations. The accelerated method provides similar results as the reference approach while offering a considerable increase in the simulation speed. However, the simulation approach may not be feasible for large (multi-million cells) designs that could benefit from static analysis methods. We benchmark the results of a static, probabilistic approach against the reference and accelerated methods. Finally, we discuss the integration of the SET analysis in a complete Soft Error Rate analysis flow.     

Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach

Nowadays, microprocessor-based system??s robustness under Single Event Effects (SEEs) represents a very important concern. A widely adopted solution to make a microprocessor-based system robust consists in modifying the application code by adding redundancy and fault tolerance capabilities. In this context, the main idea behind this paper is to evaluate a software-based technique named Optimized Embedded Signature Monitoring (OESM) using an FPGA-based fault injection technique, which is able to inject a high number of Single Event Upsets (SEUs) and Single Event Transients (SETs) in a short period of time. The obtained results demonstrated not only the increase of system??s robustness level, but also point out the remaining weak areas in the microprocessor-based system with respect to both types of SEEs.     

同步米里型序列检测电路的错误输出问题

用一般时序逻辑电路的设计方法设计米里型序列检测电路中存在一些问题,在没有检测到序列时就输出了检测到信号,系统工作出现不正常。分析了存在错误输出的原因之后,提出了一种通过调整输入序列使其与时钟同步,改进状态装换表的设计,以确保系统正常工作的米里型序列检测的设计方法,这种方法有效克服了米里型序列检测的问题,并对米里型时序逻辑电路的设计有通用性。