触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

基于概率转移矩阵的串行电路可靠度计算方法

概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够在门级比较精确地估计差错对电路可靠性影响的方法,但目前其实现方法只能适用于较小规模的电路.本文引入了电路划分的思想,先把电路分割成一组适宜用原始PTM方法直接计算其可靠度的模块,然后计算出这些模块的可靠度,再依据串行可靠度模型,将所有模块可靠度合成为整个电路的可靠度.本文用实验的方法通过对74系列电路的分析得到了合适的电路分割参数,即分割宽度,再进一步对ISCAS85基准电路进行了可靠度的计算,结果表明新方法可以适用于更大规模的无冗余组合电路.通过与依据美军标MIL-HDBK-217所算得的可靠度的比较,验证了本文所提出的方法的合理性.     

基于伯努利分布的逻辑电路可靠度计算方法

在深亚微米及纳米级集成电路设计过程中,电路的可靠性评估是非常重要的一个环节.本文提出了一种利用概率统计模型计算逻辑电路可靠度的方法,将电路中的每个逻辑门是否正常输出看作一次随机事件,则发生故障的逻辑门数为某个特定值的概率服从伯努利分布;再利用实验统计单个逻辑门出错时电路的逻辑屏蔽特性,根据此方法计算出ISCAS'85和ISCAS'89基准电路可靠度的一个特定范围.理论分析和实验结果表明所提方法是准确和有效的.     

用遗传算法实现CMOS时序电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的。实际中,总是在有限的计算时间内获取一个近似最大功耗。文中用遗传算法来选择具有高功耗的输入及内部状态模型,对电路进行仿真,实现时序电路的最大功耗估算;同时,实现了基于统计的逻辑模拟最大功耗估计方法。基于ISCAS89基准时序电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高。而且新方法的计算时间基本上是电路逻辑门的线性关系。     

CMOSVLSI电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的.由于电路功耗强依赖于其输入模式,对有大量管脚的CMOS组合或时序电路,不能采用穷举搜索.本文用遗传算法来选择具有高功耗的输入及内部状态模型,在逻辑仿真基础上实现CMOS电路的最大功耗估算.同时用逻辑仿真的统计方法来衡量获得最大功耗的质量.基于ISCAS85和ISCAS89基准电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高.而且新方法的计算时间基本上是电路逻辑门的线性关系.     

考虑信号相关性的逻辑电路可靠度计算方法

随着集成电路特征尺寸不断缩小,软错误已经成为影响电路可靠性的关键因素.计算软错误影响下逻辑电路的信号概率能辅助评估电路的可靠性.引起逻辑电路信号概率计算复杂性的原因是电路中的扇出重汇聚结构,本文提出一种计算软错误影响下逻辑电路可靠度的方法,使用概率公式和多项式运算,对引发相关性问题的扇出源节点变量作降阶处理,再利用计算得到的输出信号概率评估电路可靠度.用LGSynth91基准电路、74系列电路和ISCAS85基准电路为对象进行实验,结果表明所提方法准确有效.     

基于QCA的双边沿JK触发器的实现

量子元胞自动机(Quantum-dot Cellular Automata,QCA)是一种有望替代传统半导体晶体管的新型纳米器件.本文提出了一种改进的双边沿触发结构及其相应的JK触发器电路,用概率转移矩阵(Probabilistic Transfer Matrix,PTM)分析该触发结构,结果表明该结构较以往的可靠性更高.同时利用模块垂直堆叠方法来优化了JK触发器电路,新结构电路较之前的电路元胞数和整体面积均有所减少.     

用卡诺图分析时序逻辑电路

本文以时序电路中的同步和异步计数电路为例来说明一种用卡诺图分析时序逻辑电路的方法.1 用卡诺图分析同步时序逻辑电路写出一个电路的状态转移方程是容易的,在得到状态转移方程式以后,用卡诺图就能很快得到电路的状态编码表,同时也能够检查电路的自启动性.用卡诺图分析电路逻辑功     

高速数据采集系统中的FPGA的设计

提出了利用FPGA技术把缓存FIFO、锁存电路、时序电路、控制电路等分散的电路模块集中起来作为独立的缓存及控制电路,实现了数据的高速缓存,防止了数据丢失;产生了严格的时序逻辑,保证了系统的可靠性.利用乒乓锁存降低了对缓存速度的要求并将数据合并成32位,易于与DSP数据传输.电路模块简单可靠,易于系统调试.详细介绍了FPGA的电路模块的设计.     

基于KFDD的可逆逻辑电路综合设计方法

可逆逻辑作为量子计算,纳米技术,低功耗设计等新兴技术的基础,近年来得到了越来越多的关注和研究.然而,大多数可逆逻辑综合方法对函数真值表表达形式的依赖使得综合电路规模受到了限制.决策图作为一种更加简洁的布尔函数表示方法,其为可逆逻辑综合提供了另一种途径.本文基于Kronecker函数决策图(KFDD)提出了一种适合于综合大规模电路的综合方法.该方法利用KFDD描述功能函数,以局部最优的方式从三种节点分解方法中寻找最优分解方法,并根据Kronecker函数决策图中不同类型的节点构建相应的可逆逻辑电路模块,最后将各节点替换电路模块实现级联得到结果电路.以可逆基准电路为例,对该方法进行了验证.实验结果表明,该方法能以较低的代价实现对较大规模函数的可逆逻辑电路综合.     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.     

A graph based approach for reliability analysis of nano-scale VLSI logic circuits

Advances in nano-electronics VLSI manufacturing technology and the rapid downscaling of the size of logic circuits have made them more prone to errors. This has led to the need for fast circuit reliability evaluation of large logic circuits. In this paper a new method for reliability analysis of VLSI logic circuits based on a modified form of Mason’s rule is proposed. Utilizing matrix sparsity significantly increases the speed and reduces the required memory of the proposed approach. In addition, an approach is introduced to mitigate the effect of reconvergent paths. Simulation results indicate that the proposed method is scalable and runs 4× faster than previously proposed schemes.     

基于Pareto支配的MPRM电路面积与可靠性优化

针对MPRM（Mixed-Polarity Reed-Muller）电路的面积与可靠性折中优化问题,在逻辑级建立面积估算模型以及电路SER（Soft Error Rate）解析评价模型,并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解,并考虑多个输出之间异或门的共享,建立面积估算模型.采用信号概率和故障传播方法,并考虑电路中的逻辑屏蔽因素以及信号相关性,建立电路SER解析评价模型.根据所提出的面积和SER评价模型,采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集,并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明,与面积最小MPRM电路相比,所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

Microthyristor-based sequential circuits and systems

This paper describes the construction of new circuit configurations for some sequential circuits. These circuits are based on the microthyristor as a microelectronic bistable device that can store logic one and logic zero and on NMOS transistors that act either as pass transistors or drivers. The shift register, considered as a main type of sequential circuit, is developed from a D flip-flop that is designed basically from the microthyristor as a bistable device. Moreover, different types of counters based on the microthyristor as a storing element are developed. Microthyristor sequential circuits were found to perform well.     

Statistical static timing analysis for circuit aging prediction

Complementary metal oxide semiconductor ( CMOS) aging mechanisms including bias temperature instability ( BTI) pose growing concerns about circuit reliability. BTI results in threshold voltage increases on CMOS transistors, causing delay shifts and timing violations on logic circuits. The amount of degradation is dependent on the circuit workload, which increases the challenge for accurate BTI aging prediction at the design time. In this paper, a BTI prediction method for logic circuits based on statistical static timing analysis (SSTA) is proposed, especially considering the correlation between circuit workload and BTI degradation. It consists of a training phase, to discover the relationship between circuit scale and the required workload samples, and a prediction phase, to present the degradations under different workloads in Gaussian probability distributions. This method can predict the distribution of degradations with negligible errors, and identify 50% more BTI-critical paths in an affordable time, compared with conventional methods.     

Reliability evaluation of logic circuits using probabilistic gate models

Logic circuits built using nanoscale technologies have significant reliability limitations due to fundamental physical and manufacturing constraints of their constituent devices. This paper presents a probabilistic gate model (PGM), which relates the output probability to the error and input probabilities of an unreliable logic gate. The PGM is used to obtain computational algorithms, one being approximate and the other accurate, for the evaluation of circuit reliability. The complexity of the approximate algorithm, which does not consider dependencies among signals, increases linearly with the number of gates in a circuit. The accurate algorithm, which accounts for signal dependencies due to reconvergent fanouts and/or correlated inputs, has a worst-case complexity that is exponential in the numbers of dependent reconvergent fanouts and correlated inputs. By leveraging the fact that many large circuits consist of common logic modules, a modular approach that hierarchically decomposes a circuit into smaller modules and subsequently applies the accurate PGM algorithm to each module, is further proposed. Simulation results are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the modular PGM approach provides highly accurate results with a moderate computational complexity. It can further be embedded into an early design flow and is scalable for use in the reliability evaluation of large circuits.