Low-power survivor memory architecture for DFSE in 1000BASE-T transceiver

A novel approach to survivor memory unit of Decision Feedback Sequence Estimator （DFSE） for 1000BASE-T transceiver based on hybrid architecture of the classical register-exchange and trace-back methods is proposed. The proposed architecture is investigated with special emphasis on low power and small decoder latency, in which a dedicated register-exchange module is designed to provide tentative survivor syml~ols with zero latency, and a high-speed trace back logic is presented to meet tile tight latency budget specified for 1000BASE-T transceiver. Furthermore, clock-gating register banks are constructed for power saving. VLSI implementation reveals that, the proposed architecture provides about 40% savings in power consumption compared to the traditional register-exchange architecture.     

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.     

Algebraic survivor memory management design for Viterbi detectors

The problem of survivor memory management of a Viterbi detector is classically solved either by a register-exchange implementation which has minimal latency, but large hardware complexity and power consumption, or by a trace-back scheme with small power consumption, but larger latency. Here an algebraic formulation of the survivor memory management is introduced which provides a framework for the derivation of new algorithmic and architectural solutions. This allows for solutions to be designed with greatly reduced latency and/or complexity, as well as for achieving tradeoff between latency and complexity. VLSI case studies of specific new solutions have shown that at minimal latency more than 50% savings are possible in hardware complexity as well as power consumption     

New path history management circuits for Viterbi decoders

Up until now the trace back technique and the register-exchange approaches are two major techniques used for the path history management in the chip designs of Viterbi decoders. The former takes up less area but requires much more time than the latter, since it needs to search the trace of the survivor path back sequentially. We propose an alternate approach that is based on the concept of a permutation network and implements directly the trellis diagram of a given convolutional code. Instead of using registers to store the survivor path data, all information is recorded in a permutation network, and the resulting circuit has a smaller routing area than the register-exchange technique and has faster decoding speed than the trace-back method regardless of the constraint length. In addition, it is more straightforward to realize the permutation networks path history unit than the trace-forward unit.     

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-μm CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems     

Modified register-exchange Viterbi decoder for low-power wireless communications

In this paper, a new implementation of the Viterbi decoder (VD), based on a modified register-exchange (RE) method, is proposed. Conceptually, the RE method is simpler and faster than the trace-back (TB) method. However, the disadvantage of the RE method is that every bit in the memory must be read and rewritten for each bit of information decoded. The proposed implementation adopts the "pointer" concept: a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointer which points to the first register is altered to point to the second register. Power-dissipation, performance, memory size, and the speed of the survivor sequence management are analyzed for both the TB method, and the proposed RE method. The analysis indicates an average power reduction of 23% for the new VD, compared to the power dissipation of the VD described in the literature for the third generation of wireless applications. The bit-error rate is 10/sup -5/ with a signal-to-noise ratio of approximately 6.3 dB for a continuous, uncontrolled encoded sequence. Moreover, the memory requirements of the new implementation are reduced by half. All the read and write operations in the survivor sequence management are executed at the data rate frequency which increases the maximum frequency.     

A new architecture for the Viterbi decoder for code rate k/n

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time     

一种高速Viterbi译码器幸存路径管理模块的改进结构

针对高速Viterbi译码器的高速,低延迟,低电路复杂度的要求,在分段执行的Hybrid Trace Forward方法的基础上,提出了一种新的幸存路径管理模块(SMU)结构—固定段长的结构。对于(m,n,k)的Viterbi译码器,约束长度为k,则固定段长为k-1,既节省了存储空间,又消除了回溯过程,从而降低了延迟时间和电路复杂度。文中设计了一个(2,1,7)Viterbi译码器的SMU模块,采用固定长度为6的结构。相比于传统的分段执行的Hybrid Trace Forward结构,译码延迟减小了17%,输出数据间隔减小了33%,并且省去了存储器的使用。     

Parallel Viterbi algorithm implementation: breaking theACS-bottleneck

The central unit of a Viterbi decoder is a data-dependent feedback loop which performs an add-compare-select (ACS) operation. This nonlinear recursion is the only bottleneck for a high-speed parallel implementation. A linear scale solution (architecture) is presented which allows the implementation of the Viterbi algorithm (VA) despite the fact that it contains a data-dependent decision feedback loop. For a fixed processing speed it allows a linear speedup in the throughput rate by a linear increase in hardware complexity. A systolic array implementation is discussed for the add-compare-select unit of the VA. The implementation of the survivor memory is considered. The method for implementing the algorithm is based on its underlying finite state feature. Thus, it is possible to transfer this method to other types of algorithms which contain a data-dependent feedback loop and have a finite state property     

An Efficient Pre-Traceback Architecture for the Viterbi Decoder Targeting Wireless Communication Applications

A large portion of silicon area and the energy consumed by the Viterbi decoder (VD) is dedicated to the survivor memory and the access operations associated with it. In this work, an efficient pre-traceback architecture for the survivor-path memory unit (SMU) of high constraint length VD targeting wireless communication applications is proposed. Compared to the conventional traceback approach which is based on three kinds of memory access operations: decision bits write, traceback read, and decode read, the proposed architecture exploits the inherent parallelism between the decision bit write and decode traceback operation by introducing pre-traceback operation. Consequently, the proposed pre-traceback approach reduces the survivor memory read operations by 50%. As a result of the reduction of the memory access operations, compared to the conventional 2-pointer traceback algorithm, the size of the survivor memory as well as the decoding latency is reduced by as much as 25%. Implementation results show that the pre-traceback architecture achieves up to 11.9% energy efficiency and 21.3% area saving compared to the conventional traceback architecture for typical wireless applications.     

Survivor memory reduction in the Viterbi algorithm

This paper presents a novel approach for implementation of the Viterbi algorithm, wherein survivor paths are generally kept in as low as one half of the storage required for traditional trace-back methods. Survivor memory reduction is obtained by storing only the useful part of the survivor paths. In other words, the redundancy in the survivor paths is removed. A decoder using this approach not only requires significantly less memory, but also runs faster than conventional decoders. Some instances of this approach are explicitly presented.     

A Differential Architecture for an Online Analog Viterbi Decoder

A differential architecture of an analog Viterbi decoder is presented. Analog processing enables the analog-digital converter to be excluded from the decoder realization. Moreover, high-speed operation can be achieved via differential processing. We describe the differential operation, together with the resulting decoder structure. The differential architecture enables the trace-back memory to be excluded and makes online decoding after initial transitional stages possible. We analyze the performance of the differential analog decoder by including analog circuit nonidealities in the system-level model. The decoder obeys a nonlinear transfer function, and the monotonical growth of path metrics is avoided by scaling and subtraction of the global minimum. The resulting differential analog decoder performance is compared with the performance of a 3-bit soft-decision digital Viterbi decoder. The simulations are performed for a (2,1,7) convolutional code.     

Novel Viterbi decoder VLSI implementation and its performance

An advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation is presented. Two novel circuit design schemes have been proposed: scarce state transition (SST) decoding and direct high-coding-rate convolutional code generation and variable-rate decoding. SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading error probability performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS device. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSIs in the rate one-half mode imposed by the thermal limitation. The other Viterbi decoding scheme makes it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25-Mb/s) and universal-coding-rate Viterbi decoder VLSIs have been developed     

基于FPGA的高性能Viterbi译码器的设计与实现

对Viterbi译码器3个重要组成部分之一——幸存路径管理和存储模块进行优化设计。采用一种新的方法（改进的寄存器交换法）作为幸存路径管理方案，取消了译码时的回溯读操作。与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。在总体设计中对译码器的其他部分也进行了相应的优化设计，进行了综合布线后仿真，译码器输出的最大数据速率达到了90Mbps。     

A hybrid pipelined path-searching architecture for multiplecommunications applications

Many communications applications require similar processing functionality but are implemented independently. In particular, a number of applications (including trellis coding, encryption, and speech recognition) use techniques based on shortest path search algorithms. In this paper, we propose a high-throughput architecture that can search for the shortest path within a graph. The architecture can decode any data encoded with a finite state machine (FSM) or data encrypted in a dynamic trellis code and also serve as a specialized processor for other searching and matching applications. Balance between flexibility and hardware efficiency is achieved by an integrated design of architecture, in-place scheduling, and concurrent algorithms     

DVB-S信道内码解码器的FPGA实现

采用基于软件流水线的回溯法实现维特比译码中的幸存路径管理,从而有效节省了资源消耗,并提高了译码速度；从DVB-S解码器的整体系统结构考虑,使用一种高效的同步头锁定及内码信息确定的方案。整个设计在Xilinx公司的XC2VP30上实现。     

Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward

This brief proposes a new class of hybrid VLSI architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and traceforward algorithms, that is, low storage requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture can be efficiently applied to codes with a larger number of states where traceback-based architectures, which increase latency, are usually dominant.     

Memoryless Viterbi decoder

The problem of survival memory management of a Viterbi decoder (VD) was solved by introducing a novel pointer implementation for the register exchange method, where a pointer is assigned to each row of memory in the survivor memory unit (SMU). The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the one-pointer VD is proposed; if the initial state of the convolutional encoder is known, the entire SMU is reduced to only one row. Because the decoded data bits are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memoryless VD (MLVD), reduces the power consumption of a traditional traceback VD by approximately 50%, but has some performance degradation. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 MHz with a decoding throughput of more than 3 Mbps and a latency of two data bits.     

Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder

Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. This limitation also incurs power and silicon area overhead. This paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput     

Design of a power-reduction Viterbi decoder for WLAN applications

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-/spl mu/m standard CMOS process. The test results show that 30/spl sim/40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.