Viterbi译码的FPGA免回溯实现

卷积码在多种通信领域中广泛应用,Viterbi译码是对卷积码的一种最大似然译码算法。随着卷积码约束度的增加,并行维特比译码所需的硬件资源呈指数增长,限制其硬件实现。介绍了一种串行译码结构的FPGA实现方案,在保证性能译码的前提下有效地节省资源。同时提出了充分利用FPGA的RAM存储单元的免回溯Viterbi解码实现算法,减少了译码时延,这种算法在串行和并行译码中都可以应用。     

一种BCH码的新型译码方法及其FPGA器件实现

介绍了一种新型的BCH码的译码方法,并给出了该译码算法的FPGA器件实现方法。与传统的译码算法相比,该算法具有译码速度快、硬件实现复杂度低等优点,从而使得该译码器具有速度快、体积小、性能稳定等特点。     

通信系统中Viterbi译码的Matlab仿真与实现

数字通信作为一种前向纠错编码技术卷积码起着重要的作用。相应地,信息接收端对卷积码的译码实现也提出了更高的要求。文中提出的卷积码译码Matlab仿真方案,旨在用Viterbi译码实现对卷积码译码的功能。仿真结果表明,维特比是一种良好的译码方式。     

基于GPU的RS码并行译码算法研究

针对RS码硬件译码器中常用的BMA译码算法并行性较差,导致译码延迟较大和译码速率较低的问题,研究了RS码的高速并行译码算法及其软件实现方式,设计和实现了一种基于GPU的RS码并行译码算法cu PGZ。实验结果表明,对CCSDS建议的RS(255,223)码,在128 bits错误的情况下,cu PGZ可以达到590 Mbps的最大译码速率以及0.5 ms的最小译码延迟,与BMA算法的GPU实现相比,译码速率提高1倍,译码延迟降低为1/60。实际工程应用表明,cu PGZ能够满足实际测控数传的信道译码要求。     

软判决Fano译码算法的FPGA实现

Fano译码算法一般采用软件实现,受制于计算机的结构,译码速度较慢。为大幅度提高译码速度,研究软判决Fano译码算法的全硬件实现方案,即采用AHDL（Ahera硬件描述语言）设计软判决Fano译码译码器,使用FPGA（现场可编程门阵列）予以实现。介绍了总体结构,重点描述构建Fano软判决译码器关键部件——状态机的设计。实测数据表明,在相同时钟频率条件下,软判决Fano译码算法的全硬件实现比软件方案至少快20倍。     

卷积编译码盘的设计与实现

本文简要介绍了（2,1,3）卷积码的编译码设计与实现。编码电路可以用FPGA实现。译码采用维特比译码算法,应用高速数字信号处理器TMS320C50,实时完成高速处理任务,核心算法用软件实现。通过对算法进行分解优化,译码速度快。通过加载不同的译码软件可以在同一硬件平台上实现多种信道编译码算法。在工程中具有较高的应用价值和发展远景。     

基于MHC快速译码算法的译码树的构造方法

在传真通信中需要对数据进行压缩后再发送。一维改进的Huffman码（MHC）是在传真通信中使用较多的一种压缩编码。MHC的译码算法和快速译码算法都是通过构造译码树实现译码,但将译码树的码表应用到线性地址空间上时,都存在一定程度冲突,从而会对译码速度产生影响。文中通过对MHC快速译码算法的分析,提出了一种新的译码树构造方法,实现了在线性地址空间上对译码树的构造,并解决了原方法中的冲突问题。     

一种提高LDPC译码器吞吐率的译码算法

为了设计高效的LDPC译码器,结合准循环结构LDPC的校验矩阵H的规律性、乘性修正最小和译码算法不需要估计信道质量的特点和部分并行译码实现复杂度低的特点,介绍了一种新的译码算法——交迭的部分并行译码算法,这种译码算法相对于采用部分并行结构的BP译码算法,不但降低了硬件实现的复杂度,减少了存储资源的开销,而且提高了译码器的吞吐率。     

基于Altera Stratix的LDPC编译码器的工程实现

实现了一种相对高效的低密度校验码的编码方法,这种基于循环移位矩阵的准循环低密度校验码的设计方法既有较好的性能又有实际应用中可接受的编码复杂度。同时实现了一种高性能、低复杂度的软判决译码算法。这种译码算法较常用的硬判决译码算法性能出色,同时较一般的迭代译码算法的收敛速度快,并且可以部分并行译码,需要的存储量很小,能够大幅度降低低密度校验译码的硬件实现复杂度,具有很大的工程应用价值。     

基于多元LDPC码译码算法研究的Qt设计与实现

为了实现Qt对多元LDPC码译码算法理论测试的界面操控,在多元LDPC码译码算法研究的基础上设计了Qt程序,用Matlab实现基本仿真,将其编译成可供Qt调用的动态链接库文件(dll)并进行调用,最终实现了该Qt界面对译码理论测试的直观操控,并进一步分析了译码数据。     

MPEG-4 AAC解码器在NIOS II平台上的实现和优化

给出了MEPG-4AAC实时解码器在NIOSII平台的实现方案,介绍了MPEG-4AAC-LC解码算法及各关键模块优化算法。在完成实时解码要求下,结合NIOSII平台特性,对解码器在软件代码与处理器上进行优化。实验结果表明CPU时钟为80MHz时能达到实时解码要求。     

Decreasing energy consumption in address decoders by means of selective precharge schemes

This paper presents and evaluates three novel memory decoder designs which reduce energy consumption and delay by using selective precharging. These three designs, the AND-NOR, Sense-Amp, and the AND decoder, range in selectivity and select-line swing; these schemes charge and discharge fewer select-lines. This in turn consumes less energy than nonselective address decoders which charge and discharge all select-lines each cycle. These three decoding schemes are comprehensively simulated and compared to the conventional nonselective NOR decoder using 65 nm CMOS technology. Energy, delay, and area calculations are provided for all four 4-to-16 decoders under analysis. The most selective AND decoder performs best and dissipates between 61% and 99% less (73% less on average) and the selective Sense-Amp decoder performs only slightly worse by dissipating between 58% and 75% less (66% less on average) energy than dissipated by the NOR decoder. The AND-NOR decoder dissipates between 15% less and 20% more (6% more on average) energy than dissipated by the NOR decoder. In addition, the AND decoder is 7.5% and the Sense-Amp decoder is 5.0% faster than the NOR decoder, however, the AND-NOR decoder is 1.7% slower than the NOR decoder.     

循环汉明码编译码器的设计与FPGA实现

分析了循环码的特性,提出一种循环汉明码编译码器的设计方案。编译码器中编码采用除法电路,译码采用梅吉特译码器,易于工程应用。对编译码器在FPGA上进行了实现,通过参数化设置,具有较高的码率,适用于(255,247)及其任意缩短码的循环汉明码,并给出了译码器的仿真和测试结果。结果表明:编译码器运行速率高、译码时延小,在Virtex-5芯片上,最高工作时钟频率大于270 MHz。在码组错误个数确定的系统应用中,可以有效降低误码率,一般可将误码率降低一个量级。实践表明,该设计具有很强的工程实用价值。     

A generalized linear quasi-ML decoder of OSTBCs for wireless communications over time-selective fading channels

We propose a novel generalized linear quasi-maximum-likelihood (quasi-ML) decoder for orthogonal space-time block codes (OSTBCs) for wireless communications over time-selective fading channels. The proposed decoder computes the decision statistics based on the channel-state information and completely removes the intertransmit-antenna interference to provide excellent diversity advantage when the channel varies from symbol to symbol. It is shown that when the channel is quasi-static, the proposed decoder is the optimum ML decoder for OSTBCs. The theoretical bit-error probabilities of the proposed decoder are given and it is shown that the proposed decoder does not exhibit error floors at high signal-to-noise ratios like the decoder proposed in and . Simulation results for various channel-fading rates are presented to verify the theoretical analysis.     

一种高速自适应Reed-Solomon译码结构及其VLSI优化实现

该文给出了一种自适应Reed-Solomon(RS) 译码器结构。该结构可以自适应地处理长度变化的截短码编码数据块,适合于高速译码处理。该结构使译码处理不受数据块间隙长短的约束,既可以处理独立的编码数据块也可以处理连续发送的编码数据块。另外本译码器结构可以保证输出数据块间隔信息的完整性,满足无线通信和以太网中特殊业务的要求。本文还基于该结构对RS(255,239)译码器予以实现,该译码器经过Synopsys综合工具综合并用TSMC 0.18 CMOS工艺实现,测试结果验证了该译码器的自适应功能和译码正确性,其端口处理速率可达1.6Gb/s。     

Augmented Belief Propagation Decoding of Low-Density Parity Check Codes

We propose an augmented belief propagation (BP) decoder for low-density parity check (LDPC) codes which can be utilized on memoryless or intersymbol interference channels. The proposed method is a heuristic algorithm that eliminates a large number of pseudocodewords that can cause nonconvergence in the BP decoder. The augmented decoder is a multistage iterative decoder, where, at each stage, the original channel messages on select symbol nodes are replaced by saturated messages. The key element of the proposed method is the symbol selection process, which is based on the appropriately defined subgraphs of the code graph and/or the reliability of the information received from the channel. We demonstrate by examples that this decoder can be implemented to achieve substantial gains (compared to the standard locally-operating BP decoder) for short LDPC codes decoded on both memoryless and intersymbol interference Gaussian channels. Using the Margulis code example, we also show that the augmented decoder reduces the error floors. Finally, we discuss types of BP decoding errors and relate them to the augmented BP decoder.     

基于DXVA的多路H.264高清视频解码器的实现

设计了一种基于微软DXVA接口的H.264多路高清视频解码器。定义了代表解码器和GPU的数据结构,通过调用定义的解码函数接口,可使解码器用在各种视频播放器中。实验证明,所设计的解码器在进行多路高清解码时无论解码速度还是CPU的占用率都比传统的软件解码器有很大的性能提升。     

5G LDPC码译码器实现

该文介绍了5G标准中LDPC码的特点,比较分析了各种译码算法的性能,提出了译码器实现的总体架构：将译码器分为高速译码器和低信噪比译码器。高速译码器适用于码率高、吞吐率要求高的情形,为译码器的主体;低信噪比译码器主要针对低码率、低信噪比下的高性能译码,处理一些极限情形下的通信,对吞吐率要求不高。分别对高速译码器和低信噪比译码器进行了设计实践,给出了FPGA综合结果和吞吐率分析结果。     

A versatile time-domain Reed-Solomon decoder

A versatile Reed-Solomon (RS) decoder structure based on the time-domain decoding algorithm (transform decoding without transforms) is developed. The algorithm is restructured, and a method is given to decode any RS code generated by any generator polynomial. The main advantage of the decoder structure is its versatility, that is, it can be programmed to decode any Reed-Solomon code defined in Galois field (GF) 2^m with a fixed symbol size m. This decoder can correct errors and erasures for any RS code, including shortened and singly extended codes. It is shown that the decoder has a very simple structure and can be used to design high-speed single-chip VLSI decoders. As an example, a gate-array-based programmable RS decoder is implemented on a single chip. This decoder chip can decode any RS code defined in GF (2⁵) with any code word length and any number of information symbols. The decoder chip is fabricated using low-power 1.5-μ, two-layer-metal, HCMOS technology     

An Encoder/Decoder Scheme of OCDMA Based on Waveguide

1　ＩｎｔｒｏｄｕｃｔｉｏｎＯｐｔｉｃａｌＣｏｄｅＤｉｖｉｓｉｏｎＭｕｌｔｉｐｌｅＡｃｃｅｓｓ(ＯＣＤ ＭＡ)ｓｙｓｔｅｍｓｈａｖｅｂｅｅｎｉｎｖｅｓｔｉｇａｔｅｄ[1 ] .Ｍａｎｙｅｎ ｃｏｄｅｒｓ/ｄｅｃｏｄｅｒｓｈａｖｅｂｅｅｎ ｐｒｏｐｏｓｅｄ ,ｆｏｒｅｘａｍｐｌｅ,ｏｐｔｉｃａｌｆｉｂｅｒｄｅｌａｙ ｌｉｎｅｓ[2 ] .Ｉｎｔｈｉｓｐａｐｅｒ,ｗｅｅｍｐｌｏｙｔｈｅｌｏｗ ｗｅｉｇｈｔＯｐｔｉｃａｌＯｒｔｈｏｇｏｎａｌＣｏｄｅ(ＯＯＣ ｓ) [3～5] ｗｉｔｈｔｈｅｌｅｎｇｔｈＭａｎｄｔｈｅｗｅｉｇｈｔΩａｓｏ…