一种用于前台校准的8位高线性度DAC

设计了一种用于12位折叠插值ADC前台校准的高线性度DAC。该DAC包括电流源、开关电路、译码电路和电流-电压转换器。电流-电压转换器采用带共模反馈和增益提高技术的运放,具有高的共模抑制比和高的输出线性度。电流源的版图设计中考虑了电流源匹配特性,提出了“V”型布局方案,有效抑制其梯度误差和对称误差,提高了DAC转换线性度。在TSMC 0.18 μm CMOS工艺下对DAC进行仿真。结果表明,当输入信号频率为4.101 5 MHz、采样频率为25 MHz时,DAC的有效位数达到7.97位。     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

校准对DAC面积特性改善的研究

以一款16bit 1GS/s电流舵DAC IP为例,针对前台静态校准技术对DAC面积特性的改善进行分析研究,给出了校准技术的实现方式与相关电路。通过仿真对无校准与有校准的DAC电路进行分析比较,分别分析了有无校准的情况下小尺寸电流源管DAC的匹配特性。进一步通过版图面积分析与动态性能仿真来突出校准技术在改善电路性能,尤其是面积特性上的显著效果。     

一种10 bit电流型DAC电流源晶体管的抗失配设计

在高速高精度电流型DAC的设计中,电流源晶体管的匹配问题是设计的关键。针对10 bit DAC提出了一种对梯度误差和边缘效应不灵敏的电流源晶体管布局方案,并从单元电流源晶体管尺寸的选取到该方案具有这种特性的原因及他的具体实现都做了详细的讨论。该方案已应用于四川登巅微电子有限公司的10 bit 500 M DAC中。     

数模转换器选择指南

概述 数模转换器(又称D/A转换器或DAC)是一种将输入的数字信号转换成模拟信号输出的电路或器件。基本的DAC由电压基准或电流基准、二进制精密权电阻、一组电子开关及权电流求和电路构成。 选择一个好的DAC有三个重要标准:分辨率、准确度和转换速度。另外还要考虑其它基本要求:温度稳定性、输入编码、输出格式、基准和功耗。 DAC品种繁多、类型各异的原因是由于选择自由度数目所致。例如,工艺、功能、特性及封装形式。     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,本文设计了一种采用分段式电流舵结构的高速高精度DAC。同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响。电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能。     

一种16位高速数模转换器(DAC)的设计与实现

基于Mixed-Signal CMOS工艺,设计了一种采用分段式电流舵结构的高速高精度DAC.电路设计中同时在该DAC的内部电路中采用了一种新的电流校准技术,既保证了DAC电路的高精度,又减小了梯度误差的影响.电路流片后的实际测试结果表明,该16位DAC在400MSPS转换速率下仍具有良好的性能.     

一种应用于高速电流型DAC的电流开关驱动器

就电流开关驱动器对高速电流型DAC动态性能的影响因素进行了分析,给出了设计应对措施,并设计了一种结构简单使用了同步锁存技术、低驱动信号摆幅技术和低信号交叉点技术的电流开关驱动器电路.基于SMIC 0.18μm CMOS工艺模型,采用Hspice仿真工具,对电流开关驱动器进行仿真分析,结果表明所设计驱动器电路功能正确.测试结果表明,应用该电流开关驱动器的一款嵌入式14位400MSPS DAC电路在输出80 MHz正弦信号时,达到76.47 dB的无杂散动态范围,所设计电流开关驱动器能保证高速电流型DAC的良好动态性能.     

应用于AMOLED源极驱动的高精度DAC设计

针对OLED显示面板更高分辨率、更高精度的需求,本文提出了一种应用于高分辨率AMOLED源极驱动的高精度10bit DAC结构。设计的DAC由6bit的GAMMA校正电阻串DAC及4bit的基于尾电流源插值的输出缓冲器级联构成,达到高精度的同时占用较小的芯片面积。为进一步提高AMOLED驱动的灰阶电压精度,增加了一个DAC斜率可编程单元对线性DAC输出曲线进行进一步调节,以更好地拟合AMOLED显示屏所需的灰阶-电压曲线,此外,输出缓冲器采用尾电流源插值的方法来实现高精度的第二级DAC。在UMC 80nm CMOS工艺下,仿真结果表明设计的DAC的最大INL和DNL分别为0.47LSB、0.24LSB。在10kΩ电阻及30pF电容负载下,DAC电压从最低灰阶到最高灰阶的建立时间为3.38μs。驱动电路可以快速、精确地将图像数据转换为建立在像素电路上的电压,满足分辨率为1080×2 160驱动芯片的应用需求。     

一种16位1 GHz四开关电流舵DAC

分析了电流舵DAC中传统差分开关的缺点,采用了一种优化的四相开关结构。采用MOS电流模逻辑进行开关编码信号的限幅,以削弱电荷馈通效应。在此基础上,采用时钟交叉点配置电路,实现对DAC开关交叉点的精确控制。基于动态元件匹配译码技术,实现对电流源单元的随机调用。对该16位DAC进行了仿真和整体版图设计,其核心部分的芯片面积仅为2.2 mm²。采用0.18 μm CMOS工艺,对该DAC的性能参数进行了测试。测试结果表明,在1 GHz采样率和100 MHz输入信号频率的条件下,该DAC的无杂散动态范围约为67 dB,3阶互调失真IMD3约为76 dB,整体动态性能较好。     

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.     

基于MOCCII多功能电流模式滤波器

本文提出一种新型基于MOCCII多功能电流模式二阶滤波器电路,该滤波器电路仅由2个MOCCII及4个RC元件构成,无需元件匹配就能同时实现低通、带通、高通、带阻及全通滤波输出.该电路所有的RC元件均接地,且有很低的灵敏度.文中对滤波器的非理想特性进行了分析.最后对提出的电路进行了计算机仿真.     

Electronically tunable current-mode instrumentation amplifier with high CMRR and wide bandwidth

A current-mode instrumentation amplifier consists of only two current follower differential input transconductance amplifiers is proposed in this paper. The proposed circuit of instrumentation amplifier is realized without using any passive components. Thus, the proposed circuit structure is very simple and suitable to the integrated circuit technology. The input impedance is low and output impedance is high, therefore the proposed circuit is easily cascadable. The gain of the proposed instrumentation amplifier is electronically controllable. The proposed circuit also enjoys the features of high common mode rejection ratio, wide bandwidth and low power consumption. Additionally, performance of the proposed circuit is tested under process, supply voltage and temperature variations. Furthermore, another circuit of instrumentation amplifier, which is capable of providing higher differential mode gain is also shown. The non-ideal and parasitic studies are included. HSPICE simulations are performed to validate the proposed circuits of instrumentation amplifier.     

Novel voltage/current-mode quadrature oscillator using current differencing transconductance amplifier

This letter proposes a new realization of voltage/current-mode (CM) quadrature oscillator (QO) using Current Differencing Transconductance Amplifier (CDTA) as the active element. The proposed circuit employs canonic number of components, namely two CDTAs, one resistor and two grounded capacitors. The oscillator is capable of providing two explicit quadrature current outputs and two quadrature voltage outputs. Moreover, the circuit enjoys the advantage of independent control of condition of oscillation (CO) and frequency of oscillation (FO). The non-ideal analysis and sensitivity study of the circuit has been carried out and the circuit exhibits a good sensitivity performance. B2SPICE simulation results are included that validate the working of the circuit.     

A wideband cascaded sigma-delta modulator with improved nonlinearity effects

This work presents a wideband cascaded sigma-delta modulator (CLFSDM) that reduces the nonlinearity effects of components. This architecture offers a new noise-shaping function to achieve high resolution in wideband applications and reduce digital-analogue converter (DAC) mismatch from the multi-bit feedback. Moreover, the error cancellation schemes can be added in the digital circuit part to cancel the coarse quantization errors and thus effectively reduce the non-ideal effects such as DAC mismatch. The mismatches between the two stages, such as in the gain error and pole error, may seriously degrade performance. The blind on-line calibration technique is used to eliminate these imperfect analogue circuit errors in the digital circuit. Accordingly, this architecture can reduce the over sampling ratio (OSR), and the in-band noise can be significantly suppressed to achieve a high resolution in Matlab and Switcap2 simulations. Simulation results indicate this sigma-delta modulator is very efficient in wide bandwidth applications.     

电流型汉明神经网络的设计

本文提出了两种新的电流型汉明神经网络电路。第一种风络包括电流型模板匹配电路和全互连的电流型求大网络，结构简单，没有时钟模拟显示该电路具有高速度、高精度和低功耗等特点。在该电路的基础上，又提出了一种采用电流型模板匹配电路和电压型求大网络的汉明神经网络电路，同样具有上述特点。     

Current-Mode First-Order Allpass Filter Employing Single Current Operational Amplifier

A current-mode first-order allpass filter configuration is proposed. The presented circuit uses a single current operational amplifier (COA), a resistor and a capacitor, which are of minimum number. High output impedance of the proposed filter enables the circuit to be cascaded without additional buffers. The proposed circuit is insensitive to parasitic input capacitances and input resistances due to internally grounded input terminals of COA. It does not impose any component matching constraint in analog signal processing circuits. Non-ideal effects of COA to the first-order allpass network are also investigated. To demonstrate the performance of the proposed filter a new current-mode quadrature oscillator is given as an application example. The theoretical results are verified with PSPICE simulations using a new realization of fully differential CMOS COA.     

A current-mode bit-block circuit applicable to low-voltage, low-power pipeline video-speed A/D converters

This paper describes a study to determine if a current-mode circuit is useful as an analog circuit technique for realizing submicron mixed analog-and-digital MOS LSIs. To examine this, we designed and circuit simulated a new current-mode ADC bit-block for a 3 V, 10-bit level, 20 MHz ADC with a pipeline architecture and with full current-mode approach. A new precision current-mode sample-and-hold circuit which enables operation of a bit block at a clock speed of 20 MHz was developed. Current mismatches caused by the poor output impedance of a device were also decreased by adopting a cascode configuration throughout the design. Operation with a 3 V power supply and a 20 MHz clock speed in a 3-bit A/D configuration was verified through circuit simulation using standard CMOS 0.6 m device parameters. Gain error, mismatch of current, and linearity of the bit block with changing threshold voltage of a device were carefully examined. The bit block has a gain error of 0.2% (10-bit level), a linearity error of less than 0.1% (more than 10-bit level), and a current mismatch of DAC current sources in a bit cell of 0.2 to 0.4% (more than 8-bit level) with a 3 V power supply and 20 MHz clock speed. An 8-to 9-bit video-speed pipeline ADC can be realized without calibration. This confirms that the current-mode approach is effective.     

Design of low-power ROM-less direct digital frequency synthesizerusing nonlinear digital-to-analog converter

A design technique that uses nonlinear digital-to-analog converter (DAC) for implementing low-power direct digital frequency synthesizer (DDFS) is proposed. The nonlinear DAC is used in place of the ROM look up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS. Since the proposed design technique for DDFS does not require a ROM, significant saving in power dissipation results. The design procedure for implementing the nonlinear DAC is presented. To demonstrate the proposed technique, two quadrature DDFSs, one using nonlinear resistor string DACs and the other using nonlinear current-mode DACs, were implemented. For a 3.3-V supply, the resulting power dissipation for both DDFSs are 4 and 92 mW at a clock rate of 25 MHz and 230 MHz, respectively. For both DDFSs, the spurious free dynamic ranges are over 55 dB for low synthesized frequencies