半导体器件贮存可靠性快速评价方法

为解决复杂环境下半导体器件的贮存可靠性评估问题,结合半导体器件的贮存失效机理及其寿命-应力模型,提出了基于多贮存应力加速寿命试验的半导体器件贮存可靠性评估方法。在此基础上,以某款中频对数放大电路为研究对象,通过对加速寿命试验结果的分析,获得了电路在规定贮存时间下的可靠度。     

SOI电路可靠性筛选技术及失效机理研究

可靠性筛选是提高电子产品良率的重要技术手段。针对绝缘体上硅（SOI）技术日益广泛的应用,通过大量实验研究了SOI电路的常用筛选试验,并对失效样品进行了相应的失效机理研究。首先讨论了SOI电路失效模式和筛选方法之间的关系;其次,针对三款SOI电路分别开展了老炼应力、高温贮存及恒定加速度试验来进行可靠性筛选;最后,利用光发射显微镜、扫描电子显微镜、聚焦离子束和激励源诱导故障测试等失效分析手段,对失效样品进行了失效模式及机理分析,揭示了失效根源,为改进工艺、提高SOI电路可靠性提供了依据。     

接口混合集成电路长期工作寿命预计及验证

寿命试验常被用来评估集成电路等半导体器件的可靠性,为了节约试验时间,常采用加速寿命试验方法去评估集成电路产品的工作寿命。采用基于可靠性手册中器件失效率历史数据和基于失效物理模型两种方法对接口混合集成电路的长期工作寿命进行了预计及验证。首先,通过接口混合集成电路产品多批次寿命可靠性试验的历史数据计算出了电路工作寿命;然后,基于可靠性手册中器件失效率的历史数据、模型及其使用特性要素计算出产品的工作寿命。结果表明,两者较为接近;从而证明该类混合集成电路在加速寿命试验数据不够的情况下,采用基于可靠性手册中器件失效率数据对其进行寿命预测是可行的,为接口混合集成电路长期工作寿命评估提供了一定的参考。     

电子元器件的贮存可靠性及评价技术

综述了国内外元器件的贮存可靠性研究现状,分析了元器件贮存失效模式及原因,表明减少元器件自身缺陷、改善固有可靠性是提高其贮存可靠性的关键。并从应用性角度出发,对现场贮存、长期自然贮存试验、极限应力、加速贮存寿命试验等贮存可靠性评价技术进行了对比分析。     

单一失效机理引起的元器件贮存寿命评价方法研究

电子元器件长期贮存过程发生的失效是由多种失效机理共同作用的结果．以器件贮存寿命整体为基础的寿命评价难度很大。选择对器件贮存寿命影响最大的单一失效机理．以失效物理为基础．通过高加速应力试验进行寿命评价研究,获得的寿命可以较准确地反映器件真实的贮存寿命。单一失效机理贮存寿命的研究是元器件贮存可靠性工作的重要内容。     

半导体器件的长期贮存失效机理及加速模型

加速应力试验是评价长期贮存一次性使用半导体器件贮存可靠性的最重要途径之一.针对半导体器件不同的失效机理,选择合理、准确的加速应力模型,是定量分析半导体器件贮存寿命的基础.介绍了半导体器件在长期贮存时的主要失效机理及其加速应力模型,给出了这些模型的适用条件.     

基于加速退化晶体管贮存寿命的评估

为探求快速评价国产晶体管长期贮存寿命的方法,对国产3DK105B型晶体管开展了加速退化试验的分析和研究。通过三组不同温、湿度恒定应力的加速退化试验,确定了晶体管的失效敏感参数,利用其性能退化数据外推出样品的寿命;给出了常见的三种分布下的平均寿命,并结合Peck温湿度模型外推出自然贮存条件下本批晶体管的贮存寿命。最后分析了试验样品性能参数退化的原因。试验结果可以为评估国产晶体管的贮存可靠性水平提供一定的参考。     

脉宽调制器可靠性评估电路的设计与应用

本文介绍一种评价脉宽调制器可靠性和工艺控制水平的评估电路设计。它是针对Ｘ１５２５脉宽调制器的小批量试制和贯标而设计的。通过微电子测试图形对工艺的控制检测，和单机理失效的评估来对Ｘ１５２５４可靠性进行评价。该电路也适用于一般的双极ＩＣ的可靠性评估。文章给出了多种微电子测试图形及单机理评估电路和单元评估电路。     

长期存贮CCD的可靠性试验分析

采用外部检查和气密性检测等试验方法,对长期存贮的电荷耦合器件(CCD)的质量进行评价.对失效原因进行了分析,进而提出了在CCD的封装、贮存和运输过程中,提高CCD可靠性的具体方法,可保证其贮存寿命在10年以上.     

红外焦平面探测器贮存寿命试验研究

本文以红外焦平面探测器为研究对象,在充分分析历年来国内红外焦平面探测器贮存寿命试验数据的基础上,研究了产品的失效模式和失效机理,并对贮存寿命试验前后关键参数指标变化量进行了深入分析,为全面评价红外焦平面探测器产品质量和可靠性提供了依据,为后续红外焦平面探测器的标准制修订工作奠定了基础。     

汽车电子产品的零缺陷检测

汽车电子行业,由于高质量和可靠性要求,越来越多的客户追求零缺陷质量,零缺陷实现方法成为越来越多汽车电子制造商研究的课题.从产品设计实现、产品制造以及产品最终测试过程中,本文主要论述在产品测试检测以及数据分析中如何实现零缺陷,以及提升可靠性的老化筛选方法,有效地避免和筛选潜在失效产品的产生和流出,确保客户手中产品的零缺陷...     

Processability and reliability of nonconductive adhesives (NCAs) in fine-pitch chip-on-flex applications

The use of NCAs to form direct contact interconnections between chip bumps and substrate pads have become a viable option in interconnection technology for fine-pitch applications. However, the primary concerns with NCAs are their long-term reliability, stability, and consistent electrical performance in particulate interconnections. Results of assembly process studies and environmental testing using NCAs on flexible substrates are analyzed and discussed herein. An extensive design experiment was performed to determine which process parameters were critical in obtaining good electrical connections. A reliability evaluation of NCAs for flexible substrate applications was carried out to gain more insight into the failure mechanisms of this type of interconnect. Pressure cooker test results showed that failures occurring in NCA joints are primarily due to moisture absorption, which could lead to interfacial delamination at the substrate/adhesive interface, accompanied by hygroscopic swelling. NCAs with lower coefficients of thermal expansion also exhibited better contact resistance stability during high-temperature storage tests.     

浅析PCB两种重要可靠性测试方法

电路板可靠性评估是每个制造厂家、客户研究得最多的课题,互联应力测试及冷热循环测试是现有的在短时间内评估电路板的长期可靠性的有效测试方法。文章对互联应力测试及冷热循环测试方法及标准进行了详细介绍,并通过简单的实际测试研究案例来介绍如何分析失效并找出失效原因,并提出一些失效原因的改善方向。     

Accelerated temperature testing of transistors does not cause excess flicker noise

Electrical noise measurement analysis has been applied in reliability screening of semiconductor devices. Normally it is expected that during accelerated testing reactions increase in composition of device materials causes early failures through the process of defect production. An increase in defects is further expected to result in an increase in the noise of semiconductor devices. Accelerated temperature testing of sample of indegenous NPN transistors was done and noise was measured after certain durations of test time. No appreciable change was observed in the noise level (mainly flicker or 1/noise) even though the devices reached the stage of complete failure. This indicates that defects produced by accelerated temperature testing are not noise generators. X-ray radiography and SEM analysis study has been done for completely failed devices.     

A new built-in screening methodology to achieve zero defects in the automotive environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes logic control, high voltage generation, and leakage current monitoring.     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

Optimum software-release time considering an error-detectionphenomenon during operation

An optimal software-release problem of determining the time to stop testing and release the software system to the user is discussed. The optimality considers software error detection during not only the testing phase but also the operation phase. Two evaluation criteria for the problem are used: software reliability and mean time between failures. Numerical examples illustrate the optimal software-release problem     

Analyse des défaillances et suivi de la validation du logiciel d’un équipement de télécommunication*

This paper presents the results of the software reliability evaluation of a telecommunication equipment observed during its validation phase. Among the 2 146 collected failure reports, about 45% were discarded mainly because of the redundancy or the incompleteness of the information they contained. The statistical analysis of the selected failure reports allowed to study the classes of identified defects and their distribution among the software components and finally the failure modes. The evaluation of the software reliability measures was preceded by a trend analysis of the software reliability growth based on the Laplace test. Finally, the hyperexponential model was applied to follow up the evolution of the number of software failures during the validation phase and also to evaluate the software failure rate before the use of the system in operation with respect to the whole set of failures, and with respect to the most critical failures only.     

A New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment

Efficient screening procedures for the control of the defectivity are vital to limit early failures especially in critical automotive applications. Traditional strategies based on burn-in and in-line tests are able to provide the required level of reliability but they are expensive and time consuming. This paper presents a novel built-in reliability testing methodology to screen out gate oxide and crystal related defects in Lateral Diffused MOS transistors. The proposed technique is based on an embedded circuitry that includes control logic, high voltage generation, and leakage current monitoring. The concept, advantages and the circuit for the proposed test procedure are described in very detail and illustrated by circuit simulation.