Fabrication of high-speed InP/InGaAs/InP DHBT with a new self-aligned metallization technique for reduced base resistance

A new self-aligned emitter–base metallization (SAEBM) technique with wet etch is developed for high-speed heterojunction bipolar transistors (HBTs) by reducing extrinsic base resistance. After mesa etch of the base layer using a photo-resist mask, the base and emitter metals are evaporated simultaneously to reduce the emitter–base gap (S_EB) and base gap resistance (R_GAP). The InP/InGaAs/InP double heterojunction bipolar transistor (DHBT) fabricated using the technique has a reduced R_GAP, from 16.48 Ω to 4.62 Ω comparing with the DHBT fabricated by conventional self-aligned base metallization (SABM) process. Furthermore, we adopt a novel collector undercut technique using selective etching nature of InP and InGaAs to reduce collector–base capacitance (C_CB). Due to the reduced R_GAP, the maximum oscillation frequency (f_max) for a 0.5 μm-emitter HBT is improved from 205 GHz to 295 GHz, while the cutoff frequency (f_T) is maintained at around 300 GHz.     

改善SiGe HBT击穿电压特征频率优值的集电区优化设计

本文利用BVCES×fT代替BVCEO×fT来表征SiGe的击穿电压特征频率优值,其与SiGe HBT集电区设计更具有相关性且更具有实际意义。相比于传统通过减少集电区掺杂浓度来提高击穿电压特征频率优值,本文通过在集电极空间电荷区引入一组复合的N-和P 层来调节CB结附件的电场,降低碰撞电离率,能够在轻微损失特征频率的前提下,较大程度提高BVCES和BVCEO,进而提高了BVCES×fT和BVCEO×fT,突破了“Johnson Limit”。     

4H–SiC BJTs with current gain of 110

4H–SiC BJTs with a common emitter current gain of 110 have been demonstrated. The high current gain was attributed to a thin base of 0.25 μm which reduces the carrier recombination in the base region. The device open base breakdown voltage (BV_CEO) of 270 V was much less than the open emitter breakdown voltage (BV_CBO) of 1560 V due to the emitter leakage current multiplication from the high current gain by “transistor action” of BJTs. The device has shown minimal gain degradation after electrical stress at high current density of >200 A/cm²up to 25 h.     

Improved performance step impedance lowpass filter

Performances of the conventional Butterworth step impedance lowpass filters (LPF) are significantly improved by placing transmission zero either closer to the cut-off frequency (f_c) or away from it. It is achieved by using transverse resonance width of the capacitive line sections. We report method of designing transverse resonance type LPF (TR-LPF) for 5 to 11-pole filters. At f_c = 2.5 GHz, we obtained selectivity in the range 113.3–56.66 dB/GHz and 20–60 dB rejection BW in the range 9.61–7.29 GHz. The TR-LPF can suppress the stopband signal by 60 dB up to 5f_c. Insertion loss in passband is within 0.72 dB. Improved performance of TR-LPF can be designed for f_c up to 7.5 GHz.     

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance g_ds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an f_T of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic f_T of 165 GHz and an extrinsic f_max of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic f_T and f_max of 120 GHz and 110 GHz, respectively.     

Gain improvement and microwave operation of 4H–SiC MESFET with a new recessed metal ring structure

A new multi-recessed 4H-SiC MESFET with recessed metal ring for RF embedded circuits is proposed (MR2-MESFET). The key idea in the proposed structure is based on the elimination of the spaces adjacent to gate and stopped the depletion region extending towards drain and source and the reduction of the channel thickness between gate and drain to increase breakdown voltage (V_BR); meanwhile the elimination of the gate depletion layer extension to source/drain to decrease gate-source capacitance (C_gs). The influence of multi-recessed drift region and recessed metal ring structures on the characteristics of the MR2-MESFET is studied by numerical simulation. The optimized results show that the V_BR of the MR2-MESFET is 119% larger than that of the conventional 4H–SiC MESFET (C-MESFET); meanwhile maintain 85% higher saturation drain current. Therefore, the maximum output power density of the MR2-MESFET is 23.1 W/mm compared to 5.5 W/mm of the C-MESFET. Also, the cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of 24.9 and 91.7 GHz are obtained for the MR2-MESFET compared to 11 and 40 GHz of the C-MESFET structure, respectively. The proposed MR2-MESFET shows a maximum stable gain (MSG) exceeding 23.6 dB at 3.1 GHz which is the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

A high current gain gate-controlled lateral bipolar junction transistor with 90 nm CMOS technology for future RF SoC applications

A CMOS-compatible gate-controlled lateral BJT (GC-LBJT) was prepared with a conventional 90 nm CMOS technology for radio frequency system-on-chip (RF SoC) applications. The emitter injection efficiency and the doping profile in P-well were optimized by properly controlling source, drain, and well implants. Consequently, the GC-LBJT with a gate length of 0.15 μm can achieve a current gain over 2000 and 17/19 GHz for the f_T/f_max, respectively, which are 1000%, 200%, and 60% improvements in current gain, f_T and f_max, respectively as compared to the LBJT reported previously.     

Investigation on the thermal behavior of 0.15 μm gate-length In0.4Al0.6As/In0.4Ga0.6As MHEMT

In this study, we have successfully investigated the electrical performances of In_0.4Al_0.6As/In_0.4Ga_0.6As metamorphic high-electron-mobility transistor (MHEMT) at temperatures range from 275 K to 500 K comprehensively. By extracting the device S-parameters, the temperature dependent small signal model has been established. At room temperature, 0.15 μm T-gate device with double δ-doping design exhibits f_T and f_MAX values of 103 GHz and 204 GHz at V_ds = 1 V, an extrinsic transconductance of 678 mS/mm, and a current density of 578 mA/mm associated with a high breakdown voltage of ?13 V. Power measurements were evaluated at 40 GHz and the measured output power, linear power gain, and maximum power-added efficiency, were 7.12 dBm, 10.15 dB, and 23.1%, respectively. The activation energy (E_a) extracted from Arrhenius plots is = 0.34 eV at 150 ≦ T ≦ 350 K. The proposed device is promisingly suitable for millimeter-wave power application.     

Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET

Now a days, high-k dielectrics have been investigated as an alternative to Silicon dioxide (SiO₂) based gate dielectric for nanoscale semiconductor devices. This paper is an attempt to characterize the analog and RF performance of the high-k metal gate (HKMG) double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) in nanoscale through 2-D device simulation. The results demonstrates the impact of high-k oxide layer as single and gate stack (GS). The key idea behind this investigation is to provide a physical explanation for the improved analog and RF performance exhibited by the device. The major figures of merit (FOMs) studied in this paper are transconductance (g_m), output conductance (g_d), transconductance generation factor (g_m/I_D), early voltage (V_EA), intrinsic gain (A_V), cut off frequency (f_T), transconductance frequency product (TFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP). The effects of downscaling of channel length (L) on analog performance of the proposed devices have also been presented. It has been observed that the performance enhancement of GS configurations (k=7.5 i.e device D5 in the study) is encouraging as far as the nanoscale DG-MOSFET is concerned. Also it significantly reduces the short channel effects (SCEs). Parameters like DC gain of (91.257 dB, 43.436 dB), nearly ideal values (39.765 V⁻¹, 39.589 V⁻¹) of TGF, an early voltage of (2.73 V, 16.897 V), cutoff frequency (294 GHz, 515.5 GHz) and GTFP of (5.14×10⁵ GHz/V, 1.72×10⁵ GHz/V) for two different values of V_DS=0.1 V and 0.5 V respectively are found to be close to ideal values. Analysis shows an opportunity for realizing high performance analog and RF circuits with the device proposed in this paper i.e. device D5.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

Microwave dielectric properties of (1 − x)(Mg0.95Co0.05)TiO3– xCa0.6La0.8/3TiO3 ceramics with V2O5 addition

The microstructures and the microwave dielectric properties of the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system were investigated. In order to achieve a temperature-stable material, we studied a method of combining a positive temperature coefficient material with a negative one. Ca_0.6La_0.8/3TiO₃ has dielectric properties of dielectric constant ε_r ∼ 109, Q × f value ∼ 17,600 GHz and a large positive τ_f value ∼ 213 ppm/°C. (Mg_0.95Co_0.05)TiO₃ ceramics possesses high dielectric constant (ε_r ∼ 16.8), high quality factor (Q × f value ∼ 230,000 GHz), and negative τ_f value (−54 ppm/°C). As the x value varies from 0.1 to 0.8, (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system has the dielectric properties as follows: 21.55 < ε_r < 75.44, 21,000 < Q × f < 90,000 and −10 < τ_f < 140. By appropriately adjusting the x value in the (1 − x)(Mg_0.95Co_0.05)TiO₃–xCa_0.6La_0.8/3TiO₃ ceramic system, zero τ_f value can be achieved. With x = 0.15, a dielectric constant ε_r ∼ 25.78, a Q × f value ∼ 84,000 GHz (at 9 GHz), and a τ_f value ∼ 2 ppm/°C were obtained for 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics sintered at 1400 °C for 4 h. For practical application in communication systems, it is desirable to be able to sinter at lower temperatures. Therefore, V₂O₅ was as a sintering aid for lowering the sintering temperature of0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramics. At the same time, the 0.85(Mg_0.95Co_0.05)TiO₃–0.15Ca_0.6La_0.8/3TiO₃ ceramic system with 0.5 wt% V₂O₅ can be obtained good properties at the microwave frequencies for 1200 °C.     

K Band SiGe HBT single ended active inductors

The study of monolithic integration of active inductors (AI) on a 0.25 μm SiGe BiCMOS technology with 4 metal layers and HBTs with f_T=120 GHz is presented. Two topologies are presented and their performance discussed. Q values higher than 30 were obtained on a 3.4 GHz bandwidth at 28 GHz and maximum values as high as 100. Active inductors can be biased with low power, such as 2 V with a nominal DC current of 0.6 mA. The inductance value is controlled by external bias voltages and adjustments up to 40% were measured. Simple gyrators topologies with only 2 transistors are used for low power consumption and good performance at K Band is proved. The internal parameters of small signal model of HBT were studied and the crucial parameter to enhance the negative resistance and so the Q of the AI was identified.     

Microwave properties and applications of Y–Ba–Cu–O thin films grown on various substrates

Microwave properties of YBa₂Cu₃O_7-δ (YBCO) films grown on (100) LaAlO₃ (LAO), (110) NdGaO₃ (NGO) and (001) SrLaAlO₄ (SLAO) substrates were studied in the form of a microstrip ring resonator at temperatures above 20 K. The YBCO resonator on a SLAO substrate showed microwave properties better than or comparable to other YBCO resonators on LAO substrates. For the YBCO resonators on LAO and SLAO substrates, both Q_U and f₀ appeared to decrease as the temperature was raised. Meanwhile the resonator on a NGO substrate showed different behaviors with Q_U showing a peak at ∼70 K, which are attributed to the unique temperature dependence of the loss tangent of the NGO substrate. An X-band oscillator with a YBCO ring resonator coupled to the circuit was prepared and its properties were investigated at low temperatures. The frequency of the oscillator signal appeared to change from 7.925 GHz at 30 K to 7.878 GHz at 77 K, which was mostly attributed to the change in f₀ of the YBCO ring resonator. The signal power appeared to be more than 4.5 mW at 30 K and 2.1 mW at 77 K, respectively. At 55 K, the frequency of the oscillator signal was 7.917 GHz with the 3 dB-linewidth of 450 Hz.     

Threshold voltage instabilities in p-channel power VDMOSFETs under pulsed NBT stress

Threshold voltage instabilities induced in p-channel power VDMOSFETs by pulsed negative bias temperature stressing are presented and compared with corresponding instabilities found after the static NBT stress. Degradation observed under the pulsed stress conditions depends on the frequency and duty cycle of stress voltage pulses, and is generally lower than the one found after the static NBT stress. Optimal frequency and duty cycle ranges for application of investigated devices are proposed as well. By selecting an appropriate combination of frequency range (1 kHz < f < 5 kHz) and duty cycle (about 25%), the pulsed stress-induced ΔV_T can be reduced to a quarter of ΔV_T found after the static NBT stress.     

Operational frequency degradation induced trapping in scaled GaN HEMTs

Cut-off frequency increase from 12.1 GHz to 26.4 GHz, 52.1 GHz and 91.4 GHz is observed when the 1 μm gate length GaN HEMT is laterally scaled down to L_G = 0.5 μm, L_G = 0.25 μm and L_G = 0.125 μm, respectively. The study is based on accurately calibrated transfer characteristics (I_D-V_GS) of the 1 μm gate length device using Silvaco TCAD. If the scaling is also performed horizontally, proportionally to the lateral (full scaling), the maximum drain current is reduced by 38.2% when the gate-to-channel separation scales from 33 nm to 8.25 nm. Degradation of the RF performance of a GaN HEMT due to the electric field induced acceptor traps experienced under a high electrical stress is found to be about 8% for 1 μm gate length device. The degradation of scaled HEMTs reduces to 3.5% and 7.3% for the 0.25 μm and 0.125 gate length devices, respectively. The traps at energy level of E_T = E_V + 0.9 eV (carbon) with concentrations of N_IT = 5 × 10¹⁶cm^− 3, N_IT = 5 × 10¹⁷cm^− 3 and N_IT = 5 × 10¹⁸cm^− 3 are located in the drain access region where highest electrical field is expected. The effect of traps on the cut-off frequency is reduced for devices with shorter gate lengths down to 0.125 μm.     

Single-grain Si thin-film transistors SPICE model,analog and RF circuit applications

Single-grain thin-film transistors (SG-TFTs) fabricated inside location-controlled using μ-Czochralski process exhibit SOI-FETs like performance despite processing temperatures remaining below 350 °C. Thus, the SG-TFT is a potential technology for large-area highly-integrated electronic system and system-in-package, taking advantage of the system-on-flexible substrate and low manufacturing cost capabalities. The SG-TFT is modeled based on the BSIMSOI SPICE model where the mobility parameter is modified to fit the SG-TFT behavior. Therefore, analog and RF circuits can be designed and benchmarked. A two-stage telescopic cascode operational amplifier fabricated in a prototype 1.5 μm SG-TFT technology demonstrates DC gain of 55 dB and unity-gain bandwidth of 6.3 MHz. A prototype CMOS voltage reference demonstrates a power supply rejection ratio (PSRR) of 50 dB. With unity-gain frequency, f_T, in the GHz range, the SG-TFT can also enable RF circuits for wireless applications. A 12 dB gain RF cascode amplifier with integrated on-chip inductors operating in the 433 MHz ISM band is demonstrated.     

Computational studies on the radiative and nonradiative processes of luminescent N-heteroleptic platinum(II) complexes

Three N-heteroleptic Pt(II) complexes, [Pt(C^C)(O^O)] [O^O = acetylacetonate, C^C = 1-phenyl-1,2,4-triazol-5-ylidene (1), C^C = 4-phenyl-1,2,4-triazol-5-ylidene (2), C^C = 2-phenylpyrazine (3)] have been investigated with density functional theory (DFT) and time-dependent density functional theory (TDDFT). The radiative decay rate constants of complexes 1–3 have been discussed with the oscillator strength (f_n), the strength of spin–orbit coupling (SOC) interaction between the lowest energy triplet excited state (T₁) and singlet excited states (S_n), and the energy gaps between E(T₁) and E(S_n). To illustrate the nonradiative decay processes, the transition states between triplet metal-centered (³MC) and T₁ states have been optimized and were verified with the calculations of vibrational frequencies and intrinsic reaction coordinate (IRC). In addition, the minimum energy crossing points (MECPs) between ³MC and ground states (S₀) were optimized. At last, the potential energy curves relevant to the nonradiative decay pathways are simulated. The results show that complex 3 has the biggest photoluminescence quantum yield because the complex 3 has the biggest radiative decay rate constant and the smallest nonradiative decay rate constant in complexes 1–3.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

High-resolution wide-band LC-VCO for reliable operation in phase-locked loops

This paper presents a novel sizing scheme to implement the array of switches in the capacitor bank of LC-VCOs for oscillation frequency coarse control. The proposed scheme allows increasing the number of elements in the capacitor bank beyond the values typically achieved by binary scaling, endowing the resulting LC-VCO with a wider tuning range and high frequency resolution, which is beneficial for the implementation of reliable phase-locked loops. Two different gigahertz LC-VCOs have been designed to validate the proposed scheme. The prototypes, fabricated in a cost-effective 0.18 μm CMOS process, cover a 700 MHz frequency range from 1.35 GHz to 2.05 GHz and from 2.05 GHz to 2.75 GHz, respectively, with a phase noise figure of − 122 dBc/Hz and − 119.5 dBc/Hz at 1 MHz from the mid-range carriers, and a power consumption of 18 mW. These figures result in a respective FOM_T of − 186.4 dBc/Hz and − 183.8 dBc/Hz. The performance of the fabricated LC-VCOs is achieved in each case with a dense coarse tuning range of 128 levels, which allows, respectively, a fine tuning gain smaller than 40 MHz V^− 1.     

Low-voltage,high speed inkjet-printed flexible complementary polymer electronic circuits

We report the development of high-performance inkjet-printed organic field-effect transistors (OFETs) and complementary circuits using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and poly(methyl methacrylate) (PMMA) for high-speed and low-voltage operation. Inkjet-printed p-type polymer semiconductors containing alkyl-substituted thienylenevinylene (TV) and dodecylthiophene (PC12TV12T) and n-type P(NDI2OD-T2) OFETs showed high field-effect mobilities of 0.1–0.4 cm² V^?1 s^?1 and low threshold voltages down to 5 V. These OFET properties were modified by changing the blend ratio of P(VDF-TrFE) and PMMA. The optimum blend – a 7:3 wt% mixture of P(VDF-TrFE) and PMMA – was successfully used to realize high-performance complementary inverters and ring oscillators (ROs). The complementary ROs operated at a supplied bias (V_DD) of 5 V and showed an oscillation frequency (f_osc) as high as ～80 kHz at V_DD = 30 V. Furthermore, the f_osc of the complementary ROs was significantly affected by a variety of fundamental parameters such as the electron and hole mobilities, channel width and length, capacitance of the gate dielectrics, V_DD, and the overlap capacitance in the circuit configuration.