混沌跳频序列的设计及其性能检验

利用混沌序列产生跳频图案的方法给出了一种基于非线性数字滤波器结构的混沌跳频序列发生器的设计方案,并对产生的混沌跳频序列进行了宽间隔处理,最后对其产生的序列进行仿真性能验证.     

基于混沌的无线跳频通信技术

本文针对跳频通信以及混沌的的特点,研究了混沌跳频序列在跳频通信中的应用,建立了一种混沌序列模型,并对其产生的混沌跳频序列在以无线通信模块SHN2401为核心的家居跳频通信系统进行仿真研究.通过仿真表明该模型产生的混沌跳频序列在抗干扰和通信安全性方面具有良好的效果.     

有限精度混沌映射跳频多址序列

跳频地址码的性能对跳频多址通信系统的性能起着关键性的作用.把混沌系统引入跳频通信系统可以得到大量性能良好的跳频地址码,但是数字计算中的有限精度效应会使混沌系统的性质恶化.这里提出以m序列扰动在双精度计算条件下产生跳频多址序列,对序列的性质进行了研究.     

用于跳频多址通信的混沌跳频码

跳频码的性能对跳频多址通信起着关键性作用。设计具有良好汉明相关和随机性且数量多的跳频码是非常重要的。本文提出一种利用由混沌映射描述的离散混沌系统设计跳频码的新方法。首先由混沌映射产生混沌时间序列，然后利用量化技术对混沌时间序列进行量化，最后由量化后的混沌时间序列产生伪随机跳频码。为了增大混沌跳频码的周期和非线性复杂度，我们利用多个不同混沌映射组成一个级联混沌映射，并用来设计跳频码。实验表明，混沌跳频码具有非常好的性能。     

基于混合映射产生跳频序列的新方法

本文针对单一映射产生的跳频序列抗预测能力不强,以及由队列理论及混合映射产生的跳频序列不具有高效性,即时性差等缺点,设计出一种基于Logistic映射和Tent映射的混沌跳频序列.经过一系列的性能检验可知,这种方法产生的跳频序列除了具有良好的初值敏感性、非周期性,汉明相关性、平衡性以外,还具有即时性、高效等优良特点.因此,更适合在实际的跳频系统中应用.     

一类混沌映射扩频序列的研究

Logistic混沌映射可产生用于扩频系统的跳频序列。该文用Logistic映射构造了一个二维混沌映射,证明了该二维混沌映射轨道点的概率密度分布,提出了一种混沌跳频序列的产生方法,并通过数值仿真分析了此类扩频序列的奇、偶相关特性和序列码的平衡特性.结果表明:该混沌跳频序列具有良好的性能。     

一种组合映射产生混沌跳频序列的方法

基于Tent映射和Logistic映射,从增大混沌跳频序列的线性复杂度与增强跳频系统的安全保密性出发,提出了一种组合混沌映射产生混沌跳频序列的方法。从理论上对该跳频序列的平衡性、相关性进行了分析,并用MATLAB语言进行了数值模拟,研究表明：其模拟结果与理论分析是一致的。同时,与几种单一混沌映射所产生的混沌跳频序列进行了比较,证明了该方法是可行的。     

产生2k元伪随机序列的准混沌Mealy型有限状态机方法

该文利用m状态序列稳定的长周期,以及混沌序列流的高线性复杂度,研究了一种将m状态序列作为准混沌Mealy型有限状态机输入的 2k元伪随机序列产生方法,分析了系统的周期特性,进行了序列流随机性的测试,介绍了系统作为跳频码发生器在FPGA的仿真和综合结果。     

基于混沌的宽间隔跳频序列

提出了一种用混沌映射方法产生党间隔跳频序列的方法,分析了混沌宽间隔跳频序列的平衡特性及汉明相关特性,并讨论了序列的线性复杂度和抗破译能力。实验表明,该跳频序列性能良好,适用于短波跳频系统。     

模糊控制下的混沌跳频系统的同步

针对混沌信号的伪随机性和易于产生等特点，以改进的Logistic映射为例，用混沌序列取代跳频通信中的跳频码，给出了混沌跳频序列的神经网络实现；提出了用模糊控制的方法产生模糊随机序列，并以此控制混沌跳频系统的同步。计算机仿真结果表明，此方法是可行的，能达到良好的同步。     

A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors

Architectural verification is a critical aspect of the microprocessor design cycle. In this paper, we present a design verification environment centered around a biased random instruction generator for simulation-based architectural verification of pipelined microprocessors. The instruction generator uses biases specified by the user to generate instruction sequences for simulation. These biases are not hard-coded and can thus be changed depending on the specific areas in the design and type of design errors being targeted. Correctness checking is achieved using assertion checking and end-of-state comparison with a high-level architectural model. Several architectural-level errors are introduced into a behavioral model of the DLX processor to investigate the processor's response in the presence of design errors. Simulation experiments conducted using the behavioral model show that biased random instruction sequences provide higher coverage of RTL conditional branches and design errors than random instruction sequences or manually-generated test programs. Furthermore, instruction sequences containing a high percentage of read-after-write (RAW) and control dependencies are the most useful.     

GMW sequences (Corresp.)

The difference set design of Gordon, Mills, and Welch (GMW) is adapted for use as a pseudorandom number generator. Statistical properties of the generated binary sequences, including periodic correlation, linear span, andk-tuple statistics, are derived. One mechanization of a GMW sequence generator is suggested, and the number of sequences that can be generated with a fixed number of shift-register stages and read-only memory (ROM) size is evaluated.     

Designing security for number sequences generated by means of the sawtooth chaotic map

In the paper, we describe how to design the security of number sequences generated by a generator, exploiting the concept of partition of the state space of the sawtooth chaotic map into disjoint subspaces. We prove that the generator can generate nonperiodic and periodic sequences with arbitrary order of elements when the map is implemented in an uncountable set, and periodic sequences with arbitrary order of elements when the map is implemented in a countable set. The numerical security of the generated sequences is shown to be comparable when we limit our observations to finite time intervals. A method of designing the security of sequences produced by the generator was proposed. It was also demonstrated that the existence of methods for reconstructing the linear congruential generator does not imply automatic reconstruction of the generator, exploiting the concept of partition of the state space of the sawtooth map implemented in a finite-state machine.     

A New Approach to Analysis and Design of Chaos-Based Random Number Generators Using Algorithmic Converter

This paper presents a new approach to analysis and design of ADC-based random number generators. To this end, different full-bit and half-bit redundant stages of algorithmic converter are used to design chaotic maps. It is shown that, in the redundant and nonredundant structures, output probability density function of the converter stages and their related chaotic functions always converge to uniformity. It is demonstrated that residues become independent and uniformly distributed. This fact leads to the randomness and uniformity of distribution of the random number generator output bits. Moreover, it is shown that some common chaotic maps that are employed in chaotic random number generators can be implemented using nonredundant and half-bit redundant stages of algorithmic converter. In this way, the capability of ADC-based generators in designing chaotic maps and producing random number sequences is illustrated. The validity of the proposed chaos-based random number generator is confirmed using NIST statistical tests even in the presence of nonidealities in algorithmic converter. Since the ADCs are mixed-signal integrated circuits and can be used in high-speed applications, the ADC-based random number generator has high throughput and is easily embeddable in all analog and digital circuits.     

Design of Digital Hybrid Chaotic Sequence Generator

In theory, the chaotic mapping sequences, for example, Logistic mapping, Tent mapping, Chebyshev mapping and so on, are suitable to be used as spreading codes in a DS-CDMA system [1~4]. Most of the chaos mapping systems is analogue. However, the digital chaotic sequences are often adopted in the practical applications. There is the finite precision effect in digital chaos mapping, which has undesirable influence on the properties of the chaotic sequences (e. g. period, correlations, balanc…     

基于分组密码的跳频序列族构造

基于迭代型分组密码的理论体系,本文从工程实现的角度提出了一种用于跳频码分多址通信系统的新型跳频序列族构造方法.该算法基于密码学的加密机制,具有好的安全性和高的计算复杂度;算法的设计遵循了密码学的"混淆"和"扩散"准则,生成序列具有各项优异的性能指标.本文从安全性、随机性、均匀性、复杂度、组网特性及跳频间隔特性等各方面对产生的跳频序列进行了全面的理论分析,证明该算法具有理想的综合系统性能指标.在此基础上,利用VHDL语言设计并开发出相应的跳频加密芯片.经测试其性能稳定、运算速度快、输入方式灵活多样,已应用于实际的高速跳频通信系统中.     

基于混沌的高速随机数发生器

基于混沌的随机数发生器采用了离散时问的决定论混沌系统。决定论混沌的一个本质特征是对初始值的敏感依赖性。由于初始值是一个模拟电路的初值，对于数字测量系统是永远无法逼近或达到的，它的偏差使得测量系统产生的符号序列以后有着充分大的分离，从而使得符号序列不可预知、不可再现，具有真随机的特性。在分析了一类分段线性映射的决定论混沌系统的基本特性后，设计了由开关电容电路等组成的模拟电路。为了保证随机序列的分布特性，针对CMOS电路中主要的噪声，即MOS管的热噪声与闪烁噪声，设计时建立了二种噪声仿真模型；同时为了加快分析的效率和速度，提出了一种快速分析方法。最后，采用NIST标准进行了测试。     

Walsh Function Generators for Minimum Orthogonality Error

The design procedure of a new synchronous counter type of Walsh function generator for the generation of a set of Walsh functions with the least possible error in orthogonality is developed. Each flip-flop of the counter generates synchronously one particular Walsh function in the interval 1 of normalized time during one cycle of counting. The usual design procedures for synchronous counters are not applicable because of the large number of logic variables. Using a two-dimensional plot of the enabling inputs, it turns out that the T flip-flop is the most suitable type. It is shown that by using the symmetry properties of the enabling input patterns for a generator consisting of n T flip-flops, only (log2 n)- 1 standard time sequences, from which the remaining could be derived, need be generated. These time sequences can be easily obtained by decoding the outputs of those flip-flops generating the subset of Rademacher functions. The procedure is illustrated by taking an example of the generation of the first 16 Walsh functions.     

基于FPGA的混沌序列发生器的设计

本文提出了一种产生混沌序列的新方法:在FPGA嵌入式系统中设计了一个用于产生混沌序列的IP核。传统的混沌序列生成方法是通过软件编程实现,序列的生成速度较慢且占用资源较多。本文设计了一个IP核,利用硬件实现混沌序列的产生,提高了序列的产生速度。本文在Virtex-Ⅱ Pro开发平台上,运用EDK工具搭建了一个FPGA嵌入式平台,并添加了设计的IP核,验证了IP核的功能。     

多值“加法型”组合生成器分析

文中运用信息论原理对多值“加法型”组合生成器序列进行分析，得到钟控序列与输出序列的互信息为零的结论，证明了钟控输入与输出序列之间互信息是输出序列长度的严格递增函数，进而对控选逻辑序列设计进行分析。