Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

Dependence of gate oxide breakdown on initial charge trapping under Fowler-Nordheim injection

This work demonstrates that for constant oxide reliability stresses in the Fowler-Nordheim regime a low initial rate of charge trapping/detrapping results in long times to breakdown. It was found for MOS gate oxides that when the initial trapping has been completed at low fields times to breakdown enhance. Depending on the stress sequence measurement results can vary significantly which is of great relevance for correct oxide lifetime predictions.     

集成电路中金属连线下多晶硅电阻的不稳定性分析及抑制方法

作为集成电路的电阻单元,掺硼的多晶硅电阻在千欧级的范围内存在阻值不稳定性,尤其在金属连线下更为严重．分析了不同工艺条件下制作的多晶硅电阻电特性和晶格特性．结果表明,阻值的不稳定性主要由载流子迁移率改变引起．通过测试和运用Seto’s模型计算进一步发现,在铝连线底下势垒高度和俘获的电荷密度均有降低．电荷的俘获／反俘获在多晶硅晶粒边界发生引起势垒高度的变化,从而导致阻值不稳定．然后,借助于补偿的离子注入制作了高稳定的、阻值在千欧级的多晶硅电阻．该方法使得多晶硅晶粒边界电荷的俘获／反俘获对氢退火不敏感．     

Gate bias polarity dependence of charge trapping and time-dependentdielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm² for substrate injection, but less than 30 C/cm² for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q _BD in excess of 50 C/cm² is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

In this paper, the current hysteresis of organic thin film transistors (OTFTs) formed by TIPS-Pentacene has been demonstrated by bi-directional gate-voltage scan and explained using the trapping and detrapping mechanism. The trapping and detrapping rates have been further verified by the gate-voltage sampling method and the channel charge pumping method. The validity of the methods to characterize interface states of OTFTs that lead to the hysteresis is justified. The two independent methods consistently reveal that the hole trapping and release rates at the interface between the channel of the OTFTs to the gate dielectric are asymmetric.     

Study of gate oxide leakage and charge trapping in ZMR and SIMOXSOI MOSFETs

Characterization of gate oxides grown on zone-melting-recrystallized (ZMR) and silicon-implanted-with-oxygen (SIMOX) films indicates oxide leakage and charge trapping to be several orders of magnitude greater than their bulk silicon counterparts. Electron trapping is the primary trapping mechanism for constant current injection in the gate oxides of these SOI (silicon-on-insulator) films. Similar type of traps are observed in ZMR and SIMOX oxides     

High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model     

Reversibility of charge trapping and SILC creation in thin oxides after stress/anneal cycling

The reversibility of charge buildup and SILC generation in thin oxides subjected to successive stress/anneal cycles is investigated. It is demonstrated that in thin oxides both electron trapping and SILC are nearly fully reversible degradation processes having a generation kinetics almost unchanged after several stressing/annealing cycles. The annealing kinetics of the SILC is likely associated to the out diffusion of charged defects (possibly trapped holes or H+) whose characteristics (diffusivity, activation energy) are independent of the oxide thickness. Moreover correlation between electron trapping and SILC generation has been studied.     

Characterization of charge trapping and high-field endurance for15-nm thermally nitrided oxides

Device-quality gate oxides have been nitrided using both rapid thermal processing and conventional furnace treatment. Charge trapping and high-field endurance including breakdown field and time-dependent dielectric breakdown, are investigated in detail. It is found that proper nitridation can eliminate positive charge accumulation in oxides, increase charge to breakdown, suppress high-field injection-induced interface state generation, and decrease the dependence of the breakdown field on the gate area as a result of the reduced density of microdefects. Experimental results show that although both the density and capture cross-section of the bulk and interface traps increased by nitridation, the combined effects of bulk and interface traps induced by high-field injection can improve the stability of the flatband voltage. For lightly nitrided oxides, the trap generation rate is greatly decreased as compared with the as-grown oxide. Not only are the density and capture cross-section of the traps affected by nitridation, but also the locations of the trapped-charge centroids are changed. The experimental results for postnitridation annealing suggest that these property modifications most likely result from nitridation-induced structural changes rather than hydrogenation alone     

High-field breakdown in thin oxides grown in N2O ambient

A detailed study of time-dependent dielectric breakdown (TDDB) in N₂O-grown thin (47-120 Å) silicon oxides is reported. A significant degradation in breakdown properties was observed with increasing oxide growth temperatures. A physical model based on undulations at the Si/SiO₂ interface is proposed to account for the degradation. Accelerated breakdown for higher operating temperatures and higher oxide fields as well as thickness dependence of TDDB are studied under both polarities of injection. Breakdown under unipolar and bipolar stress in N₂O oxides is compared with DC breakdown. An asymmetric improvement in time-to-breakdown under positive versus negative gate unipolar stress is observed and attributed to charge detrapping behavior in N₂O oxides. A large reduction in time-to-breakdown is observed under bipolar stress when the thickness is scaled below 60 Å. A physical model is suggested to explain this behavior. Overall, N₂O oxides show improved breakdown properties compared with pure SiO₂     

Experimental Evidence of the Fast and Slow Charge Trapping/Detrapping Processes in High- k Dielectrics Subjected to PBTI Stress

A single-pulse technique, with a wide range of pulse times, has been applied to study positive bias temperature instability in high-k nMOSFETs. It is shown that the charging phenomenon includes both fast and slow electron trapping processes with rather well-defined characteristic times, which differ by six orders of magnitude. On the other hand, the poststress charge relaxation cannot be described by a simple detrapping process, which makes identifying the dominant detrapping mechanism complicated.     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

基于PVK/PbS纳米晶有机无机复合薄膜电双稳器件性能研究

通过简单旋涂方法,制备了一种基于硫化铅（PbS）纳米晶与聚乙烯基咔唑（PVK）的有机/无机复合薄膜电双稳器件,并对所制备的器件进行性能测试及其电荷传输机制研究。首先采用热注入的方法制备了尺寸均一的立方形PbS纳米晶,然后将PbS纳米晶与PVK聚合物混合作为活性层材料,制备了有机/无机复合薄膜电双稳器件。该器件展示了良好的电双稳特性并且可以实现稳定的“读-写-读-擦”操作。器件的最大电流开关比能够达到10⁴。并进一步对器件在正向电压下的I-V曲线进行了理论拟合,发现在不同电流传导状态下,器件符合不同的电传导模型。进而分析了该电双稳器件中的电荷传输机制,认为在电场的作用下,发生在纳米晶与聚合物之间的电场诱导电荷转移是产生电双稳特性的主要原因。     

Multiple-Scale Analysis of Charge Transport in Semiconductor Radiation Detectors: Application to Semi-Insulating CdZnTe

The transport, trapping, and subsequent detrapping of charge in single crystals of semi-insulating cadmium zinc telluride (CdZnTe) has been analyzed using multiple-scale perturbation techniques. This method has the advantage of not only treating impulse charge generation typical in spectroscopic analysis, but also a large class of continuous generation sources more relevant to high-flux x-ray imaging applications. We first demonstrate that the multiple-scale solutions obtained for small-current transients induced by an impulse generation of charge are consistent with well-known exact solutions. Further, we use the multiple-scale solutions to derive an analytic generalization of the Hecht equation that incorporates detrapping over times much longer than the carrier transit time (i.e., delayed signal components). The method is then applied to a continuous charge generation source that approximates that of an x-ray source. The space–time solutions obtained are relevant to detector design in high-flux x-ray imaging applications. Throughout this work the multiple-scale solutions are compared with exact solutions as well as full numerical solutions of the fundamental charge conservation equations.     

Transient charge and current distributions in the nitride of MNOS devices

Transient charge distributions in the nitride of MNOS devices at constant-current pulses have been computed using the pronounced detrapping model of Arnett. The results are compared with available analytical expressions for the limiting cases of small injected-charge levels and the steady state. Centroid versus charge content is computed and fitted by an analytical expression containing three parameters which are related to the electron range before trapping, the steady-state occupied-trap concentration at the oxide boundary, and the Frenkel-Poole coefficient. Charge outflow into the gate electrode is computed and used to obtain the apparent centroid as derived from the shift of flat-band voltage with injected charge.     

The dielectric reliability of intrinsic thin SiO2films thermally grown on a heavily doped Si substrate—characterization and modeling

The dielectric reliability of the intrinsic thin SiO2films (∼ 110 Å) thermally grown on heavily doped n-type Si substrates has been studied by using the time-zero-dielectric-breakdown (ramp-voltage-stressed I-V) and time-dependent-dielectric-breakdown (constant-voltage-stressed I-t and constant-current-stressed V-t) tests. These experiments have been performed to investigate the variations of trapped electron density, interface state density, and field enhancement in a thin SiO2film stressed with different amounts of Charges. Moreover, the temperature effects on these parameters in a thin SiO2film have also been studied. A theoretical model considering the effects of dynamic trapping (i.e., trapping and detrapping), positive charge generation, weak spots, and robust area is proposed to describe the conduction mechanism and dielectric breakdown of a thin SiO2film. Important physical parameters such as barrier height, trapped electron density, trap capture cross section, and trap generation rate have been analyzed to interpret the temperature effects.     

Impact of high tunneling electric fields on erasing instabilities in NOR flash memories

Experimental data and analysis show that overerase effects in NOR Flash memories increase with the electric field used during erasing. We found that the electric field is an accelerating factor for cell degradation during cycling. Tunnel oxide degradation reaches a critical level above which the cell starts showing erased threshold voltage instabilities possibly leading to single bit failure. Experimental data show that cell degradation during erasing has to be ascribed to hole injection rather than to electron injection and that both hole trapping and detrapping increase with the electric field. The total stress time required to reach the critical degradation level has been found to follow a 1/E/sub ox/ exponential dependence which is similar to the oxide breakdown phenomena thus establishing a physical link between the two phenomena. Anode Hole Injection has been suggested as hole generation and injection mechanism occurring during erasing and it is shown to be consistent with the experimental data.     

Thin polyoxide films grown by rapid thermal processing

The growth of thin (80-200 Å) oxide films by rapid thermal processing (RTP) on LPCVD poly and amorphous silicon is reported. Oxide growth kinetics are affected by dopant concentration, implant species, and preoxidation anneal conditions. Breakdown fields > 11 MV/ cm have been measured. Constant current stress measurements indicate a higher rate of negative charge trapping in oxides grown on top of polysilicon as compared to amorphous silicon.     

Electrical observation of deep traps in high-/spl kappa//metal gate stack transistors

The instability of threshold voltage in high-/spl kappa//metal gate devices is studied with a focus on the separation of reversible charge trapping from other phenomena that may contribute to time dependence of the threshold voltage during a constant voltage stress. Data on the stress cycles of opposite polarity on both pMOS and nMOS transistor suggests that trapping/detrapping at the deep bandgap states contributes to threshold voltage instability in the pMOS devices. It is found that under the same electric field stress conditions, threshold voltage changes in pMOS and nMOS devices are nearly identical.