Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-a-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.     

Mo/Al/Mo结构电极的坡度角和关键尺寸差研究

Mo/Al/Mo结构金属作为TFT的电极,刻蚀后的坡度角和关键尺寸差是重要的参数。明确影响坡度角和关键尺寸差的工艺参数,进而控制坡度角和关键尺寸差,这对工艺制程至关重要。本文探究了膜层结构、曝光工艺、刻蚀工艺对坡度角和关键尺寸差的影响,并对刻蚀工艺进行正交试验设计。实验结果表明:Al膜厚每减小60nm,坡度角下降约9°,关键尺寸差增加0.1μm。曝光工艺中,显影后烘烤会增加光阻粘附力,导致关键尺寸差减小0.1μm,同时坡度角增加约9°。刻蚀工艺中,过刻量每增加10%,坡度角下降3.3°,关键尺寸差增加0.14μm;正交试验结果表明,对关键尺寸差、刻蚀均一性、坡度角影响因素的重要性顺序是:液刀流量Air Plasma电压水刀流量。经上述探究表明,坡度角和关键尺寸差呈负相关关系,刻蚀程度增加,关键尺寸差增加,而坡度角则减小。可以通过调节工艺参数对坡度角和关键尺寸差进行控制。     

The advantages of radical distribution control and independent dual frequency on etch/ash

The transition to 65 nm beyond and 300 mm wafers posed many challenges on etch depth and critical dimension (CD) uniformity within wafer. In this paper, we introduce a radical distribution control (RDC) system for an excellent uniformity control.Etch depth and CD uniformity within wafer are well controlled by adding RDC function to SCCMTM. For increasing productivity, an all-in-one process, that is, etch/ash at the same chamber continuously is proposed here. By utilizing the advantage of independent dual frequency, a bias-controlled two-step ash "hybrid ash" is combined in the all-in-one process. Hybrid ash uses bias control and low pressure to minimize liner loss and the damage of low-k materials, which is targeting 65nm and beyond.     

Reactor characterization for a process to etchSi3N4 formed on thin SiO2

A plasma etching process for patterning LPCVD (low-pressure chemical vapor deposition) Si₃N₄ which has been formed on thin thermally grown SiO₂ has been developed and characterized with an Applied Materials 8110 batch system using 100-mm-diameter silicon wafers. To fulfill the primary process objectives of minimal critical dimension (CD) loss (~0.08 μm), vertical profiles after etch, retention of some of the underlying thermal SiO₂, and batch etch uniformity, the reactor has been characterized by evaluating the effects of variation of reactor pressure (15 to 65 mTorr), O₂ concentration by flow rate (30 to 70%) of an O₂/CHF₂ mixture, and DC bias voltage (-200 to -550 V). Analysis of the resulting etch rate, etch uniformity, dimensional, and profile data suggests that satisfactory processing may be achieved at low reactor pressure (~25 mTorr), 50-60% O₂ by flow rate in O₂/CHF₃, and low DC bias (-200 to -250 V)     

微测辐射热计器件工艺开发和特性评估

依托半导体生产线开发了基于MEMS微桥结构的微测辐射热计(micro-bolometer)器件,其中,使用化学气相沉积(CVD)技术开发了非晶硅(α-Si)薄膜工艺,并将其用作微测辐射热计器件的敏感层材料,该材料在1 000?厚度下的膜厚均匀性可以控制在2%以内(1-sigma,within wafer),电阻均匀性可以控制在2%以内(1-sigma,within wafer),其室温下的电阻温度系数(TCR)可以达到-2.5%左右;采用先刻沟槽工艺技术开发了MEMS微桥结构的接触模块,以无支撑柱结构实现了其支撑和电连接结构;使用Ti/TiN薄金属薄膜作为电极层,并利用电极层图形实现该敏感层电阻器件的电连接和图形定义;开发了高性能敏感层电阻工艺技术,实现了对敏感层材料工艺损失和电极层侧面腐蚀的良好工艺控制。在完成微测辐射热计器件工艺开发后,对其进行了器件级测试和评估,结果表明：该器件室温电阻值在250 kΩ左右,且具有优异的欧姆接触特性;室温下器件级TCR在-2%左右,略低于非晶硅薄膜材料TCR的测试值;同时,对该器件进行的升温和降温测试结果表明,文中开发的敏感层材料没有滞回效应。最后...     

Modeling magnetically enhanced RIE of aluminum alloy films usingneural networks

Aluminum (Al) and its alloy films are widely used for fabricating VLSI interconnections. The discharge behavior of a magnetically enhanced reactive ion etching (MERIE) of Al(Si) has been modeled using neural networks. A 2^6-1 fractional factorial experiment was employed to characterize etch variations with RF power, pressure, magnetic field and gas mixtures of Cl₂, BCl₃, and N₂. Responses of an Al(Si) film etched in a chlorine-based plasma include etch rate, selectivity to oxide, anisotropy and bias of critical dimension (CD). The generalization accuracy of the models, measured by the root-mean squared error (RMS) on a test set, are 285 Å/min for etch rate, 5.58 for oxide selectivity, 0.08 for anisotropy, and 3.82 Å/min for CD bias. Al(Si) etch rate was found to be chlorine-dependent with significantly affected by magnetic field variations. For the other etch responses, RF power was dominant. Gas additives such as BCl₃ and N₂ were seen to have conflicting effects on etch outputs. Predicted Al(Si) etch behaviors from neural process models were in qualitative good agreement with reported experimental results     

Plasma Etching for Sub-45-nm TaN Metal Gates on High-k Dielectrics

Etching of TaN gates on high-k dielectrics (HfO₂ or HfAlO) is investigated using HBr/Cl₂ chemistry in a decoupled plasma source (DPS). The patterning sequence includes 248-nm lithography, plasma photoresist trimming, etching of a SiN-SiO₂ hard mask, and photoresist stripping, followed by TaN etching. TaN etching is studied by design of experiment (DOE) with four variables using a linear model with interactions. It is found that at a fixed substrate temperature and wafer chuck power, etch critical dimensions (CD) gain decreases with decreasing HBr/Cl₂ flow rate ratio and pressure and with increasing source power and total gas flow rate. Based on these DOE findings, subsequent optimization is performed and a three-step etching process is developed; a main feature of the process is progressively increasing HBr/Cl₂ flow rate ratio. The optimized process provides etch CD gain within 2 nm and gate profile close to vertical and reliable etch-stop on high-k dielectric. This process is successfully applied to the fabrication of the 40-nm HfAlO/TaN gate stack p-MOSFETs with good electrical parameters     

Stabilization of sheet resistance for metal lines by formation of etch stop layer (ESL) trench structure

Sheet resistance of metal lines is mainly affected by critical dimension (CD), etch depth, and chemical mechanical planarization amount in damascene process. Therefore, these factors must be stably controlled in order to stabilize the sheet resistance of metal lines. Especially the etch depth, which is sensitive to the pattern density and the equipment conditions bring not only the variation of sheet resistance of metal lines but also the connection problem to the under-layered contacts. The objective of this study is to reduce the variation of the sheet resistance of metal lines by stabilization of the etch depth with etch stop layer (ESL). SiN film was used as an ESL while the intermetal dielectric (IMD) films were employed by the conventional fluorine-doped silicate glass (FSG)/SiH₄ film with an increment of thickness by the employment of SiN film as an ESL. The selectivity of oxide-to-nitride was about 6.4:1 for etch stop step. While the stop layers were removed after the etch stop step, the pre-metal dielectric was also etched at the same time for the stable connection to the under-layered contacts. Comparing the ESL method to the conventional method, more stable metal lines were formed with the in-line CD measurement, thickness measurement, cross-sectional scanning electron microscopy analysis, and sheet resistance measurement from the view point of the connection to the under-layered contacts. The stable sheet resistance of metal lines was also obtained with the changes in etch time or thickness.     

Development of a magnetron-enhanced plasma process for tungstenetchback with response-surface methodology

A two-step etchback process to form tungsten plugs in submicron contacts and vias has been developed. the process uses an Applied Materials Inc., P5000 WCVD magnetron-enhanced, single-wafer system with an experimental design and response-surface methodology. Tungsten is first etched with an Ar/SF₆ mixture until excited N₂ molecules from the underlying TiN adhesion layer are detected in the plasma. Residual TiN is then etched for a fixed time with an Ar/Cl ₂ plasma. Both steps employ a rotating 0.5-Hz magnetic field. Although the use of the magnetic field has no pronounced effect on the etch rate of either film, it provides broad regions of high etch uniformity. In addition, the DC-bias voltage measured as part of the TiN study decreases with increasing magnetic field strength without reducing the etch rate of the film     

动态蚀刻补偿法在减成法板上的应用

采用DES线制作PCB外层线路时,线宽精度影响因素主要有表面铜厚度及铜厚均匀性、蚀刻均匀性/稳定性、线路密集程度差异、菲林补偿差异等。首先对DES线设备、工艺参数优化;其次在设备参数正常条件下研究发现当表面铜厚均匀性相同时,表面铜厚越厚则线宽差距越大,即铜厚每相差10 m则线宽相差10 m~20 m;然后深入研究发现68.6 m表面铜厚的密集线、孤立线线宽差异约25.4 m。最后确立密集线、孤立线差异的消除方法为"引入Genesis2000的动态蚀刻补偿功能对菲林补偿优化";并通过批量验证其补偿法则是准确的及使用该软件是可行的、有效的,提高了酸性蚀刻制作外层减成法板线宽精度。     

氮化硅的ECCP刻蚀特性研究

本文对氮化硅的增强电容耦合等离子刻蚀进行研究,为氮化硅刻蚀工艺的优化提供参考。针对SF_6+O_2气体体系,通过设计实验考察了功率、压强、气体比、氦气等对刻蚀速率和均一性的影响,并对结果进行机理分析和讨论。实验结果表明:功率越大,刻蚀速率越大,与源极射频电力相比,偏置射频电力对刻蚀速率的影响更为显著;压强增大,刻蚀速率增大,但压强增大到一定程度后,刻蚀速率基本不变,刻蚀均匀性随着压强增大而变差;在保证SF_6/O_2总流量保持不变下,O_2的比例增大,刻蚀速率先增大后减小,刻蚀均匀性逐步变好;He的添加可以改善刻蚀均匀性,但He的添加量过多时,会造成刻蚀速率降低。     

Processing and Characterization of Dry-Etch Benzocyclobutene as Substrate and Packaging Material for Neural Sensors

Electrode substrate is one of the most important factors affecting the recording or stimulation efficiency and long-term stability of chronically implanted neural sensors for laboratory research. Various biocompatible polymers have been investigated as potential substrate and packaging material for neural sensors in neuroscience research applications. Dry-etch benzocyclobutene (BCB) is one candidate due to its desirable combination of electrical, mechanical, and thermal properties and its biocompatibility. In this paper, processing techniques were investigated to control the uniformity and pin-pole density of dry-etch BCB film. Dry-etch BCB film as thick as 25 mum with a surface roughness less than 1000 A and a pinhole density less than 1.5 x 10^-3 mm^-2 has been acquired using an optimized coating and curing recipe. A traditional surface micro-machining technique was used to form the metallization and etch masks during the fabrication of the neural electrode based on dry-etch BCB substrate. Special consideration was given to the study of dry-etch BCB thin film patterning using plasma reactive ion etching dry etching. The optimized plasma etch condition shows that greater than 1 mum etch rate and 65deg via angle are the most suitable for the packaging and patterning of the neural probes. The results show that this fabrication process is optimal for chronically implantable neural sensors based on dry-etch BCB thin film as substrate. The process may find applications in other devices using BCB as substrate.     

Spatial characterization of wafer state using principal componentanalysis of optical emission spectra in plasma etch

Optical emission spectroscopy (OES) is often used to obtain in-situ estimates of process parameters and conditions in plasma etch processes. Two barriers must be overcome to enable the use of such information for real-time process diagnosis and control. The first barrier is the large number of measurements in wide-spectrum scans, which hinders real-time processing. The second barrier is the need to understand and estimate not only process conditions, but also what is happening on the surface of wafer, particularly the spatial uniformity of the etch. This paper presents a diagnostic method that utilizes multivariable OES data collected during plasma etch to estimate spatial asymmetries in commercially available reactor technology. Key elements of this method are: first, the use of principal component analysis (PCA) for dimensionality reduction, and second, regression and function approximation to correlate observed spatial wafer information (i.e., line width reduction) with these reduced measurements. Here we compare principal component regression (PCR), partial least squares (PLS), and principal components combined with multilayer perceptron neural networks (PCA/MLP) for this in-situ estimation of spatial uniformity. This approach has been verified for a 0.35-μm aluminum etch process using a Lam 9600 TCP etcher. Models of metal line width reduction across the wafer are constructed and compared: the root mean square prediction errors on a test set withheld from training are 0.0134 μm for PCR, 0.014 μm for PLS, and 0.016 μm for PCA/MLP. These results demonstrate that in-situ spatially resolved OES in conjunction with principal component analysis and linear or nonlinear function approximation can be effective in predicting important product characteristics across the wafer     

A novel in situ monitoring technique for reactive ion etching usinga surface micromachined sensor

This paper presents a novel technique for monitoring film thickness in reactive ion etching by incorporating a micromachined sensor. The prototype sensor correlates film thickness with the change in resonant frequency that occurs in a micromachined platform during etching. The platform is suspended over a drive electrode on the surface of the substrate and electrically excited into resonance. As material is etched from the platform, its resonant vibrational frequency shifts by an amount proportional to the amount of material etched, allowing etch rate to be inferred. As a proof-of-concept experiment, a platform made of DuPont 2611 polyimide has been fabricated. The sensor is driven into resonance electrostatically, and the shift in resonance is detected by monitoring the change in impedance between the drive electrode and platform as the drive frequency is swept. To enhance filtering of the sensor signal in the noisy plasma environment, the platform is designed so that the ratio of the plasma frequency to the fundamental mode of vibration is approximately 400:1. The prototype was etched in a Plasma Therm 700 series reactive ion etching (RIE) system in a CHF₃/O₂ plasma. Electrical contact was made with the sensor using a feedthrough attached to the vacuum line beneath the process chamber to facilitate in situ excitation and measurement. The sensor is shown to offer high resolution (approximately 1300 Hz/um), potentially permitting accurate in situ monitoring of etch rate and uniformity at a nominal cost     

Supervisory run-to-run control of polysilicon gate etch using insitu ellipsometry

Polysilicon gate etch is a critical manufacturing step in the manufacturing of MOS devices because it determines the tolerance limits on MOS circuit performance. The etch used in the current study suffers from machine aging, which causes processing results to drift with time. Performing the etch for the same time with fixed process setpoints (recipe) for all wafers would produce unsatisfactory results. Thus, an in situ ellipsometer was employed with a new run-to-run supervisory controller, termed predictor corrector control (PCC), to eliminate the impact of machine and process drift. A novel modeling technique was used to predict uniformity from the ellipsometry data collected at a single site on the wafer. Predictive models are employed by the PCC supervisory controller to generate optimal settings (recipe) for every wafer which will achieve a target mean etch rate, while maintaining a spatially uniform etch. A 200 wafer experiment was conducted to demonstrate the benefits of process control. Implementation of PCC resulted in a 36% decrease in standard deviation from target for the mean etch rate. In addition, the data indicates that controlling etch rate may improve the control and uniformity of the line width change     

HgCdTe探测列阵干法技术的刻蚀形貌研究

首次报道了HgCdTe微台面焦平面探测列阵成形工艺的干法刻蚀技术有关刻蚀形貌的一些研究结果.从HgCdTe外延材料的特点出发,详细分析了其干法刻蚀适用的RIE(reactive ion etching)设备和刻蚀原理.采用高等离子体密度、低腔体工作压力、高均匀性和低刻蚀能量的ICP(inductively coupled plasma)增强型RIE技术,研究了不同的工艺气体配比、腔体工作压力、ICP源功率和RF源功率对HgCdTe材料刻蚀形貌的影响,并初步得到了一种稳定的、刻蚀表面清洁、光滑、图形轮廓良好、均匀性较好和刻蚀速率较高的干法刻蚀工艺.     

TaN wet etch for application in dual-metal-gate integration technology

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O_3/H_2O and NH_4OH/H_2O_2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO_3/H_2O solution due to HF being included in HF/HNO_3/H_2O, and the fact that TaN is difficult to etch in the NH_4OH/H_2O_2 solution at the first stage due to the thin TaO_xN_y layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO_3/H_2O solution first and the NH_4OH/H_2O_2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and J_g-V_g characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.     

Characterization of physical-chemical drivers of Hg1−xGdxTe etch rate using time of flight—Secondary ion mass spectrometry and optical interferometry

Time of flight-secondary ion mass spectrometry (TOF-SIMS) is a Hg_1−xCd_xTe surface diagnostic tool with unprecedented analysis capabilities, including analyzing a 0.5-μm diameter spot, high mass resolution, elemental and molecular composition scrutiny, applicability to insulators, and surface film sensitivity in the part per million range. The present investigation demonstrates the power of TOF-SIMS when coupled with optical interferometry in understanding process reproducibility and uniformity critical to the fabrication of Hg_1−xCd_xTe detector arrays at RVS. Previous published works and unpublished studies at RVS have shown that geometry and fluid dynamics influence the lateral uniformity of surface chemistry, topography, and etch rates. By combining a set of photolithographically delineated features having various relative areas of photoresist-coated and uncoated regions in varying proximity to each other with various wet etching chemistries, we have exploited TOF-SIMS interrogation along with optical interferometry to investigate physical-chemical drivers of etch rate variation with window geometry orientation with respect to vertical gravity etchant fluid draining direction and proximity to other structures. This study has given us the ability to deconvolve two important etch rate drivers (depletion of etchant species and cross-contamination of etched windows) and elucidate their roles in enhancing and diminishing etch rates for features having far and close proximities to neighboring structures, respectively. This information allows a more judicious optimization of processing technology.     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

Implementation of tungsten metallization in multilevelinterconnection technologies

The techniques of experimental design and response-surface methodology have been used to produce empirical models of the deposition and etchback of tungsten in commercially available reactors for a tungsten plug technology. Deposition was carried out in a Genus 8402 LPCVD (low-pressure chemical vapor deposition) batch reactor by the H ₂ reduction of WF₆. Response-surfaces for deposition rate, sheet resistance uniformity, resistivity, and film stress were developed as a function of reactor pressure, reactor temperature, and flow rate of WF₆ at a fixed H₂ flow rate using linear-interactive models. A thin layer of TiN was used to ensure adhesion of tungsten to SiO₂. Etchback of the composite layer of W/TiN to form via plugs was performed in a Tegal 804 single-wafer system with a two-step process using mixtures of SF₆ with C₂F₆ and He with Cl₂ in step 1 and step 2, respectively. Process parameters for both steps were obtained from quadratic models of etch rate and etch uniformity