A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

A 1 K×1 K high dynamic range CMOS image sensor with on-chipprogrammable region-of-interest readout

An integrated 1024×1024 CMOS image sensor with programmable region-of-interest (ROI) readout and multiexposure technique has been developed and successfully tested. Size and position of the ROI is programmed based on multiples of a minimum readout kernel of 32×32 pixels. Since the dynamic range of the irradiance normally exceeds the electrical dynamic range of the imager that can be covered using a single integration time, a multiexposure technique has been implemented in the imager. Subsequent sensor images are acquired using different integration times and recomputed to form a single composite image. A newly developed algorithm performing the recomputation is presented. The chip has been realized in a 0.5-μm n-well standard CMOS process. The pixel pitch is 10 μm² and the total chip area is 164 mm ²     

Monolithic CCD imagers in HgCdTe

Charge-coupled device (CCD) infrared detector arrays in 5 μm cutoff HgCdTe have been demonstrated for low background applications. These fully monolithic 128 by 28 element CCD arrays incorporate time-delay-and-integrate (TDI) detection, serial readout multiplexing, charge-to-voltage conversion and buffer amplification in the HgCdTe detector chip. Operation of these devices at 77 K have produced average detectivity values exceeding 3×10¹³ cm-Hz^1/2/W for a background flux level of 6×10¹² photon/cm²-sec in the 3.0 μm to 5.5 μm spectral band. Overall performance data indicates the monolithic HgCdTe CCD to be a promising alternative to present midwave infrared hybrid focal plane array technology     

A multimode digital detector readout for solid-state medicalimaging detectors

A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate ΣΔ analog-to-digital converter (ADC) to measure current over a 130-dB dynamic range in a 1 kHz band and resolve charge pulses down to 360 e^- at 100 000 events/s. Detector currents of up to 7 μA and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 μm complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm² and dissipates 11 mW/channel from a 5 V supply     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies     

新型电流镜积分红外量子阱探测器读出电路的设计分析

设计了一种偏压可调电流镜积分(Current Mirroring Integration,CMI)红外量子阱探测器焦平面CMOS读出电路。该电路适应根据偏压调节响应波段的量子阱探测器,其中探测器偏压从0.61 V到1.55V范围内可调。由于CMI的电流反馈结构,使得输入阻抗接近0,注入效率达0.99;且积分电容可放在单元电路外,从而可以在一定的单元面积下,增大积分电容,提高了电荷处理能力和动态范围;为提高读出电路的性能,电路加入撇除(Skimming)方式的暗电流抑制电路。采用特许半导体(Chartered)0.35 m标准CMOS工艺对所设计的电路(16×1阵列)进行流片,测试结果表明:在电源电压为3.3V,积分电容为1.25pF时,电荷处理能力达到1.3×107个电子;输出摆幅达到1.76V;功耗为25mW;动态范围为75dB;测试结果显示CMI可应用于高性能FPA。     

A 7.5-ns 32 K×8 CMOS SRAM

A 256 K (32 K×8) CMOS static RAM (SRAM) which achieves an access time of 7.5 ns and 50-mA active current at 50-MHz operation is described. A 32-block architecture is used to achieve high-speed access and low power dissipation. To achieve faster access time, a double-activated-pulse circuit which generates the word-line-enable pulse and the sense-amplifier-enable pulse has been developed. The data-output reset circuit reduces the transition time and the noise generated by the output buffer. A self-aligned contact technology reduces the diffused region capacitance. This RAM has been fabricated in a twin-tub CMOS 0.8-μm technology with double-level polysilicon (the first level is polycide) and double-level metal. The memory cell size is 6.0×11.0 μm² and the chip size is 4.38×9.47 mm ²     

一个128×128CMOS快照模式焦平面读出电路设计

本文介绍了一个工作于快照模式的CMOS焦平面读出电路新结构——DCA(Direct-injection Charge Amplifier)结构.该结构像素电路仅用4个MOS管,采用特殊的版图设计并用PMOS管做复位管,既可保证像素内存储电容足够大,又可避免复位电压的阈值损失,从而提高了读出电路的电荷处理能力.由于像素电路非常简单,且该结构能有效消除列线寄生电容C_bus的影响,因此该结构非常适用于小像素、大规模的焦平面读出电路.采用DCA结构和1.2μm双硅双铝(DPDM-Double-Poly Double-Metal)标准CMOS工艺设计了一个128×128规模焦平面读出电路试验芯片,其像素尺寸为50×50μm²,电荷处理能力达11.2pC.本文详细介绍了该读出电路的体系结构、像素电路、探测器模型和工作时序,并给出了精确的HSPICE仿真结果和试验芯片测试结果.     

Memory array architecture and decoding scheme for 3 V only sectorerasable DINOR flash memory

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V_cc and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 μm, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8×1.6 μm² and the chip measures 5.8×5.0 mm ². The divided bit line structure realizes a small NOR type memory cell     

一种高性能红外焦平面阵列读出电路

提出了一种快闪式红外焦平面阵列读出电路。采用改进的直接注入型单元电路,积分电容大小可选,能适应大范围的光背景条件,并且增加了图像变换(倒置/反转)功能。一款128×128阵列的读出电路已经基于标准0.5μmCMOS工艺实现,整体芯片的面积为8.0mm×8.5mm。实测结果表明,此读出电路具有良好的光电转换能力,同时具有功耗低、输出摆幅大、动态范围大等优点。     

A 50-MHz 8-Mbit video RAM with a column direction drive senseamplifier

An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm², and the chip area is 12.7×16.91 mm²     

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-μm CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71×1.20 μm ², and the chip size is 15.91×9.06 mm². A typical access time under 3.3 V power supply voltage is 29 ns     

An 8-bit-resolution, 360-μs write time nonvolatile analog memorybased on differentially balanced constant-tunneling-current scheme(DBCS)

This paper describes a fast and accurate nonvolatile analog memory (NVAM) and its programming scheme. Both constant programming rate and single-pulse programmability have been achieved, which drastically enhance programming speed and accuracy. A prototype chip containing 8×128 NVAM cells (cell size of 9×13.6 μm²) has been fabricated using 0.8-μm CMOS. Each cell is measured to store more than eight bit levels within 360 μs     

Deep cryogenic noise and electrical characterization of thecomplementary heterojunction field-effect transistor (CHFET)

This paper discusses a characterization at 4 K of the complementary heterojunction field-effect transistor (CHFET), to examine its suitability for deep cryogenic (<10 K) readout electronics applications. The CHFET is a GaAs-based transistor analogous in structure and operation to silicon CMOS. The electrical properties including the gate leakage current, subthreshold transconductance, and input-referred noise voltage were examined. It is shown that both n-channel and p-channel CHFET's are fully functional at 4 K, with no anomalous behavior, such as hysteresis or kinks. Complementary circuit designs are possible, and a simple CHFET-based multiplexed op-amp is presented and characterized at 4 K. The noise and gate leakage current of the CHFET are presently several orders of magnitude too large for readout applications, however. The input-referred noise is on the order of 1 μV/√(Hz) at 100 Hz for a 50×50 μm n-channel CHFET. The gate current is strongly dependent on the doping at the gate edge, and is on the order of 10^-14 A for a 10×10 μm ² n-channel CHFET with light gate-edge region doping     

一种低压新型曲率补偿基准电压源设计

基于Chrt0.35 μmCMOS工艺,设计了一种基于亚阈值工作区的一阶温度补偿和I²_PTAT电路组成的带隙基准电压源。芯片测试结果表明,电路在1.2 V电源电压下便可工作;在温度-20~120 ℃范围内,基准电压源平均温度系数＜2×10^-6/℃。该带隙基准源具有良好的可应用于高精度模数转换器(ADC)、数模转换器(DAC)和系统集成芯片(SOC)中。     

Fabrication of buried channel waveguides in fused silica usingfocused MeV proton beam irradiation

Low-loss channel waveguides have been fabricated in fused silica using a beam of MeV protons focused down to a spot size of several microns. By using a combination of beam and sample scanning, single- and multimode graded index waveguides with lateral dimensions down to approximately 5 μm×5 μm have been fabricated using ion doses in the range (3×10¹⁴)-(6×10¹⁶) ions/cm ². Typical beam currents in the range 100 pA-10 nA were used. Optical mode profiles have been measured at 670 nm and propagation losses of the order of 3 dB/cm measured in unannealed samples. Annealing the substrate for 1 h at 500°C reduced these losses to below 0.5 dB/cm     

Low-power clock-deskew buffer for high-speed digital circuits

An IC containing four clock deskew buffers using the delay-locked-loop technology has been fabricated in a 0.6 μm single poly double metal CMOS process. The core chip area is 0.9×0.9 mm ². The maximum operating frequency is 80 MHz, and the total power dissipation of the four deskew buffers is 59 mW for a 3 V supply voltage. The maximum clock skew after deskewing is less than 300 ps, and the peak-to-peak clock jitter is less than 170 ps. The deskew range is 0.5-3.8 ns     

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the cascode current mirror (with current ratio of 1:10) can increase charge sensitivity and reduce integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits