A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed.The relevant parameter analysis and the details of circuit design are presented.The test chip was implemented in a TSMC 0.18μm 1P4M RF CMOS process.The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz.The measured noise figure is around 1.5-1.7 dB on both bands.The LNA consumes less than 4.3 mA of current ...     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

A low spur,low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop(PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs(1 kHz to 10 MHz);the phase noise is-89 ...     

A low spur, low jitter 10-GHz phase-locked loop in 0.13-μm CMOS technology

This paper presents a 10-GHz low spur and low jitter phase-locked loop (PLL).An improved low phase noise VCO and a dynamic phase frequency detector with a short delay reset time are employed to reduce the noise of the PLL.We also discuss the methodology to optimize the high frequency prescaler's noise and the charge pump's current mismatch.The chip was fabricated in a SMIC 0.13-μm RF CMOS process with a 1.2-V power supply.The measured integrated RMS jitter is 757 fs (1 kHz to 10 MHz); the phase noise is -89 and-118.1 dBc/Hz at 10 kHz and 1 MHz frequency offset,respectively; and the reference frequency spur is below -77 dBc.The chip size is 0.32 mm2 and the power consumption is 30.6 mW.     

Low‐noise,low‐voltage,low‐power IF gain controlled amplifiers for wireless communication

Circuit solutions of various types of gain controlled IF amplifiers with digital and analog gain control are described. Advantages and disadvantages of the different solutions are shown. Requirements for lowpower, lowvoltage, low noise, high gain and linearity at high IFfrequencies from the system point of view are worked out. Solutions will be presented to optain optimum performance by technology and circuit design technique for digital wireless telephone systems used for GSM and PCN systems.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

5.18–7.42 GHz LC-VCO in subthreshold regime with low power low phase noise and immunity to PVT variations in 130 nm CMOS technology

In this paper, we propose an LC-VCO using automatic amplitude control and filtering technique to eliminate frequency noise around 2\(\omega _0\). The LC-VCO is designed with TSMC 130 nm CMOS RF technology, and biased in subthreshold regime in order to get more negative transconductance to overcome the losses in the LC-Tank and achieve less power consumption. The designed VCO operates at 5.17 GHz and can be tuned from 5.17 to 7.398 GHz, which is corresponding to 35.5% tuning range. The VCO consumes through it 495–440.5 \(\upmu\)W from 400 mV dc supply. This VCO achieves a phase noise of \(-\,122.3\) and \(-\,111.7\) dBc/Hz at 1 MHz offset from 5.17 and 7.39 GHz carrier, respectively. The calculated Figure-of-merits (FoM) at 1 MHz offset from 5.17 and 7.39 GHz is \(-\,199.7\) and \(-\,192.4\) dBc/Hz, respectively. And it is under \(-\,190.5\) dBc/Hz through all the tuning range. The FoM\(_T\) at 1 MHz offset from 5.17 GHz carrier is \(-\,210.6\) dBc/Hz. The proposed design was simulated for three different temperatures (\(-\,55\), 27, \(125\,^{\circ }\hbox {C}\)), and three supply voltages (0.45, 0.4, 0.35 V), it was concluded that the designed LC-VCO presents high immunity to PVT variations, and can be used for multi-standard wireless LAN communication protocols 802.11a/b/g.     

A 52?pJ/bit 433-MHz low power OOK transmitter

An OOK transmitter in 433-MHz ISM band employing a speed-up circuit is described. The proposed speed-up circuit accelerates the start-up of the oscillator and buffer by briefly increasing the bias currents during transmission of bit “1”. This leads to a data rate increase from 3 to 10-Mb/s without any penalty on power consumption. The data rate can also be made adaptable by varying the duration in which the bias current is increased. The proposed OOK transmitter is implemented in 0.35-μm CMOS technology. The measured results show that the transmitter achieves a maximum data rate of 10-Mb/s with a dc power consumption of 518 μW from a 1-V power supply, yielding an energy efficiency of 52 pJ/bit or 0.97 nJ/bit/mW when normalized to the output power. This paper also derives a closed form equation which describes the transient behavior of Colpitts oscillator during start up.     

A low power high gain gain-controlled LNAC＋mixer for GNSS receivers

A low power high gain gain-controlled LNAC+mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load.Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNACmixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNAC+mixer, a previous low power LNAC+mixer, and the proposed LNAC+mixer are presented. The circuit is implemented in 0.18 m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2and consumes 2 mA current under 1.8 V supply.     

Analysis of a low magnetic field TE m11 gyroklystron amplifier†

Large- and small-signal numerical calculations are presented for a two-cavity, low magnetic field gyroklystron amplifier operating in the TE _m11 whispering-gallery mode. The gyroklystron system modelled consists of a bunching cavity and an output cavity separated by a drift tube. For operation of both cavities at TE₅₁₁, gain and emission efficiency are studied for a high energy (γ = 1·6), low axial velocity (β_Verbar; = 0·1) electron beam. Prebunching prior to the output cavity in the gyroklystron leads to an increase of the maximum efficiency by more than a factor of two over that obtained from operating the output cavity as an oscillator. Model calculations are presented which show that magnetic field tapering greatly reduces the effects of any initial axial velocity spread in the electron beam, allowing high gain (?40 dB) and high efficiency (25-30%) to be achieved.     

Ultra low power frequency divider for 2.45 GHz ZigBee frequency synthesizer

An ultra low power CMOS frequency divider whose modulus can be varied from 481 to 496 is presented. It has been customized to be used in 2.45 GHz Integer-N PLL frequency synthesizers utilized in ZigBee standard. Its based on swallow divider that replaces the swallow counter by a simple digital circuit in order to reduce power consumption and design complexity. Also a low power and high speed divide-by-7/8 is presented. Post layout simulation results exhibit 420 μW power consumption for 4 bit frequency divider in 2.45 GHz ISM frequency band that proves 40 % reduction compared to same previous works. All of the circuits have been designed in 0.18 μm TSMC CMOS technology with a single 1.8 V DC voltage supply.     

A 0.18μm CMOS Gilbert low noise mixer with noise cancellation

正This paper presents a broadband Gilbert low noise mixer implemented with noise cancellation technique operating between 10 MHz and 0.9 GHz.The Gilbert mixer is known for its perfect port isolation and bad noise performance.The noise cancellation technique of LNA can be applied here to have a better NF.The chip is implemented in SMIC 0.18μm CMOS technology.Measurement shows that the proposed low noise mixer has a 13.7-19.5 dB voltage gain from 10 MHz to 0.9 GHz,an average noise figure of 5 dB and a minimum value of 4.3 dB.The core area is 0.6 x 0.45 mm~2.     

Investigation of nanometer-scale films using low angle X-ray reflectivity analysis in IPOE

The X-ray low angle reflectivity measurement is used to investigate single and bilayer films to determine the parameters of nanometer-scale structures,three effectual methods are presented by using X-ray reflectivity analysis to provide an accurate estimation of the nanometer film structures. The parameters of tungsten (W) single layer, such as the material density, interface roughness and deposition rate, were obtained easily and speedily. The base metal layer was introduced to measure the profiles of single low Z material film. A 0.3 nm chromium (Cr) film was also studied by low angle reflectivity analysis.     

A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications

A 5-bit lumped CMOS step attenuator with low insertion loss and low phase distortion is designed and simulated in this paper. The proposed attenuator is based on lumped switched bridged-T and π structure attenuators, and implemented with 0.18-μm CMOS technology. Different attenuation states are controlled by NMOS switches. The switches in series branches have channel-shunt resistance to minimize the on-resistance without increasing parasitic capacitance. The NMOS switches in shunt branches are body-floated to improve the power handling performance of the proposed attenuator. Each attenuation module has an inductive phase-compensate low-pass network. The attenuator is controlled with a 5-bit digital signal to achieve the maximum attenuation amplitude range of 0–31 dB with 1 dB increase at 3–22 GHz. The root mean square (RMS) amplitude errors for each one of the 32 states are less than 0.53 dB and the RMS insertion phase is less than 6.3° at 3–22 GHz. The insertion loss is 5.5–13 dB, and the input P_1 dB is 18.4 dBm at 12.5 GHz.     

BEOL工艺综合Integration—low—k Dual／Damascene的形成

1简介当前,从成膜方法来讲,ILDlow-k材料大致上分为两类:一类是以SiCOH为代表的CVD(化学气相淀积)膜,另一类是SOD(旋转涂层)膜,它包括有机的、无机的和SiCOH。从IC制造者的角度来看,low-k材料的选择是一项艰难的工作,因为选择low-k材料,不能只考虑膜材料的性能,还需要考虑它与铜的结合以及DualDamascene统合等情况。当把low-k材料用于铜互联系统时,不仅需要解决许多技术问题,而且还有许多与CoO/CoC有关的问题。我们从单工程和整体工程Integration结合着手,提出了一些解决办法。对low-k膜来说,为了降低CoC,建议采用RSC(Reduced…     

Time-based all-digital sigma–delta modulators for nanometer low voltage CMOS data converters

A phase-based delta?Csigma (????) analog-to-digital converter (ADC) is proposed and the idea is demonstrated using two architectures. The first architecture adopts a delay-locked-loop (DLL) mechanism. It is realized by a modification of a DLL using a voltage-controlled delay line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ???? ADC achieved 50.5?dB SNDR or 8.09?bits resolution for a 10?MHz signal bandwidth. The second architecture adopts a combination of voltage-controlled and digitally-controlled delay lines (VCDL?CDCDL) as the phase-domain counterparts of an ADC?CDAC in a traditional delta?Csigma modulator. Simulation results of the new modulator achieve a 57.8?dB SNR, or a 9.28 bit over a 10?MHz bandwidth.     

Sol–gel deposited SiO2 and hybrid low dielectric constant thin films

The paper presents the comparative analysis of effect of hydrochloric (HCl), hydrofluoric (HF) acid catalyst and organic material methylmethacrylate (MMA) on dielectric constant of thin films. The dielectric constant of thin film obtained by using HCl catalyst is 3.63 which have been successfully reduced to 2.97 for hybrid thin films via incorporation of carbon. The deposited low k dielectric thin films observed to have good adhesion with p-silicon substrate and hence pertinent for interlayer dielectric (ILD) in ultra-large scale integrated (ULSI) circuits applications. The deposited films have been characterized by ellipsometer for refractive index, further material compositions have been studied by using Fourier transform infrared (FTIR) spectroscopy and energy dispersive spectroscopy (EDAX).