Effect of interface states on electron transport in 4H-SiCinversion layers

The effect of trapping in interface states on channel conductance and field-effect mobility in SiC MOSFETs is studied experimentally and theoretically. Hall effect measurements in n-channel MOS devices with varying densities of interface states were used to determine the effect of trapping on carrier mobility. The dependence of electron mobility on immobile interfacial charge density was quantified and was found to be similar to that in silicon, provided that the mobility is normalized to μ₀, the value in the absence of Coulomb scattering. A relationship has been established between the ratio of field-effect mobility to the actual carrier mobility and the density of interface states at the Fermi energy     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

Some Critical Materials and Processing Issues in SiC Power Devices

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO₂ interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.     

Extraction of SiO2/SiC interface trap profile in 4H- and 6H-SiC metal-oxide semiconductor field-effect transistors from subthreshold characteristics at 25°C and 150°C

The profile of trap density at the SiO₂/SiC interface in SiC metal-oxide semiconductor field-effect transistors (MOSFETs) is critical to study the channel electron mobility and evaluate device performance under various processing and annealing conditions. In this work, we report on our results in determining the interface trap density in 4H- and 6H-SiC MOSFETs annealed in dry O₂, NO, and CO₂, respectively, based on the device transfer and currentvoltage characteristics in the subthreshold region at 25°C and 150°C. We also studied electron field-effect mobility, fixed oxide charge, and gate leakage in those devices.     

Comment on A. Agarwal and S. Haney, “Some Critical Materials and Processing Issues in SiC Power Devices” [J. Electron. Mater. 37, 646 (2008)]

Agarwal and Haney [J. Electron. Mater. 37, 646 (2008)] have recently suggested that bulk defects may limit the inversion-layer mobility in SiC metal oxide semiconductor field-effect transistors. However, we believe that the physics of charge trapping and Coulomb scattering by bulk traps quantitatively contradicts this model.     

4H-SiC隐埋沟道MOSFET迁移率的研究

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

Study of Electron Mobility in 4H-SiC Buried-Channel MOSFETs

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

耗尽型4H-SiC埋沟MOSFET器件解析模型研究

建立了基于漂移扩散理论的4H-SiC埋沟MOSFET器件的物理解析模型。SiC/SiO_2界面处的界面态密度及各种散射机制都会导致器件载流子迁移率的下降,采用平均迁移率模型,分析散射机制对载流子迁移率的影响,讨论了界面态对阈值电压的影响。考虑到器件处在不同工作模式下,沟道电容会随栅压的变化而改变,采用了平均电容概念。器件仿真结果表明:界面态的存在导致漏极电流减小;采用平均迁移率模型得到的计算结果与实验测试结果较为一致。     

Effect of processing conditions on inversion layer mobility and interface state density in 4H−SiC MOSFETs

N-channel, inversion mode MOSFETs have been fabricated on 4H−SiC using different oxidation procedures, source/drain implant species and implant activation temperature. The fixed oxide charge and the field-effect mobility in the inversion layer have been extracted, with best values of 1.8×10¹² cm⁻² and 14 cm²/V-s, respectively. The interface state density, D_it close to the conduction band of 4H−SiC has been extracted from the subthreshold drain characteristics of the MOSFETs. A comparison of interface state density, inversion layer mobility and fixed oxide charges between the different processes indicate that pull-out in wet ambient after reoxidation of gate oxide improves the 4H−SiC/SiO₂ interface quality.     

SiC-MOS界面优化的工艺验证及MOSFET电学特性仿真拟合

SiC因其优越的电学特性,已发展成为高压功率器件领域的翘楚。然而,SiC与SiO₂界面存在高密度界面态,使得SiC MOSFET沟道迁移率远低于SiC材料本身的体迁移率,大大约束了SiC材料本身电学性能的发挥。为改善反型层沟道迁移率,不同功率器件厂商采用了不同的栅极氧化工艺,所实现的栅极氧化层界面态密度各有不同,现有的功率器件仿真软件提供的多种界面态能级分布模型都需要芯片厂商实际的流片数据作为支撑,这对功率器件上游设计人员产生了阻碍。基于此,文章通过流片测试数据,结合TCAD仿真软件给出了一种用于SiC MOSFET器件仿真的界面态能级分布模型。利用给出的界面态能级分布模型,与实际产品对比,仿真得出的I-V曲线与测试曲线基本重合。     

Electron-Scattering Mechanisms in Heavily Doped Silicon Carbide MOSFET Inversion Layers

Hall-effect measurements of n-channel MOS devices were used to determine the main scattering mechanisms limiting mobility in SiC MOSFETs. MOS-gated Hall characterization, which was performed as a function of gate bias and body bias, indicates that surface-roughness scattering and Coulomb scattering are the main scattering mechanisms limiting electron mobility in SiC MOSFETs at room temperature. A charge-sheet model, including incomplete ionization and Fermi-Dirac statistics, is used to calculate the surface electric fields in order to develop an expression for surface-roughness scattering. In the samples used for this paper, at electron sheet densities less than 1.8times10¹² cm^-2, Coulomb scattering dominates, while surface roughness is dominant at higher sheet densities.     

SiC power-switching devices-the second electronics revolution?

Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

Thermal Boundary Resistance Between GaN and Substrate in AlGaN/GaN Electronic Devices

The influence of a thermal boundary resistance (TBR) on temperature distribution in ungated AlGaN/GaN field-effect devices was investigated using 3-D micro-Raman thermography. The temperature distribution in operating AlGaN/GaN devices on SiC, sapphire, and Si substrates was used to determine values for the TBR by comparing experimental results to finite-difference thermal simulations. While the measured TBR of about 3.3 x 10^-8 W^-1 ldr m² ldr K for devices on SiC and Si substrates has a sizeable effect on the self-heating in devices, the TBR of up to 1.2 x 10^-8 W^-1 ldr m² ldr K plays an insignificant role in devices on sapphire substrates due to the low thermal conductivity of the substrate. The determined effective TBR was found to increase with temperature at the GaN/SiC interface from 3.3 x 10^-8 W^-1 ldr m² ldr K at 150degC to 6.5 x 3.3 x 10^-8 W^-1 ldr m² ldr K at 275degC, respectively. The contribution of a low-thermal-conductivity GaN layer at the GaN/substrate interface toward the effective TBR in devices and its temperature dependence are also discussed.     

Stacked pentacene layer organic thin-film transistors with improvedcharacteristics

Using two layers of pentacene deposited at different substrate temperatures as the active material, we have fabricated photolithographically defined organic thin-film transistors (OTFTs) with improved field-effect mobility and subthreshold slope. These devices use photolithographically defined gold source and drain electrodes and octadecyltrichlorosilane-treated silicon dioxide gate dielectric. The devices have field-effect mobility as large as 1.5 cm²/V-s, on/off current ratio larger than 10⁸, near zero threshold voltage, and subthreshold slope less than 1.6 V per decade. To our knowledge, this is the largest field-effect mobility and smallest subthreshold slope yet reported for any organic transistor, and the first time both of these important characteristics have been obtained for a single device     

Significantly improved performance of MOSFETs on silicon carbideusing the 15R-SiC polytype

Recent studies regarding MOSFETs on SiC reveal that 4H-SiC devices suffer from a low inversion layer mobility, while in 6H-SiC, despite a higher channel mobility the bulk mobility parallel to the c-axis is too low, making this polytype unattractive for power devices. This work presents experimental mobility data of MOSFETs fabricated on different polytypes as well as capacitance-voltage (C-V) measurements of corresponding n-type MOS structures which give evidence that the low inversion channel mobility in 4H-SiC is caused by a high density of SiC-SiO₂ interface states close to the conduction band. These defects are believed to be inherent to all SiC polytypes and energetically pinned at around 2.9 eV above the valence band edge. Thus, for polytypes with band gaps smaller than 4H-SiC like 6H-SiC and 15R-SiC, the majority of these states will become resonant with the conduction band at room temperature or above, thus remarkably suppressing their negative effect on the channel mobility. In order to realize high performance power MOSFETs the results reveal that 15R-SiC is the best candidate among all currently accessible SiC polytypes     

A new hole mobility model for hydrodynamic simulation

A new self-consistent hole mobility model that includes the lattice and the hole temperature has been proposed. By including the lattice and hole temperatures as well as the effective transverse field and the interface fixed charge, the model predicts the saturation of the hole drift velocity and shows the effects of Coulomb scattering, surface phonon scattering, and surface roughness scattering. The model has been incorporated into a device simulation program, SNU-2D. The simulation results have been compared with the reported experimental data and the measured 0.1 μm pMOSFETs, and they are shown to agree quite well. The new model is expected to estimate the characteristics of very short-channel devices in the hydrodynamic model simulations.     

Materials and Applications for Solution-Processed Organic Field-Effect Transistors

Organic field-effect transistors (FETs) are presently attracting significant academic research and industrial development interests as they offer performance capabilities comparable to those of thin-film amorphous silicon transistors but at the same time are compatible with low-temperature solution/printing-based manufacturing on flexible plastic substrates. In this paper, we review recent materials advances to improve the field-effect mobility of solution-processed organic semiconductors, discuss recent insight into the physics that determines the electronic structure at the semiconductor-gate dielectric interface in these devices, and provide an overview over some of the near- and medium-term applications.