Qualifying Serial Interface Jitter Rapidly and Cost-effectively

High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen in a communication interface, Bit Error Rate (BER) performance is of paramount importance. The bit errors in HSSIs are in large part due to jitter. This paper investigates the topic of accelerating the jitter and BER testing. We first present an under-sampling based transmitter test scheme. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100 ms while the test usually takes seconds. Then we propose a jitter tolerance extrapolation algorithm that enables us to perform the receiver jitter tolerance characterization and production test more than 1,000 times faster. The transmitter and receiver testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with data rates up to 6 Gigabits per second (Gbps). The paper also presents a low cost external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay line. With the novel jitter injection scheme and an FPGA-based Bit Error Rate Tester (BERT), we can validate and test HSSIs with higher data rates, but without the need of high-speed ATE instruments. Using high-speed relays, we can also utilize ATE to provide a more versatile scheme for HSSI validation, characterization and testing.     

Jitter tolerance calibration for high-speed serial interfaces

A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI standard specification. As an example, the proposed solution is applied for the jitter tolerance simulation and characterization of the most updated M-PHY ver.3 HSSI standard for mobile applications. A comprehensive method for the calculation of the jitter noise frequency ingredients and the calibration of jitter noise sources is also proposed resulting a jitter tolerance mask compliant with the M-PHY ver.3 specifications. Using the proposed implementation the transistor level and behavioral modules co-simulation time could be significantly minimized.     

A 20 Gb/s triple-mode (PAM-2, PAM-4, and duobinary) transmitter

Increasing data rates over electrical channels with significant frequency-dependent loss is difficult due to excessive inter-symbol interference (ISI). In order to achieve sufficient link margins at high rates, I/O system designers implement equalization in the transmitters and are motivated to consider more spectrally-efficient modulation formats relative to the common PAM-2 scheme, such as PAM-4 and duobinary. This paper reviews when to consider PAM-4 and duobinary formats, as the modulation scheme which yields the highest system margins at a given data rate is a function of the channel loss profile, and presents a 20 Gb/s triple-mode transmitter capable of efficiently implementing these three modulation schemes and three-tap feed-forward equalization. A statistical link modeling tool, which models ISI, crosstalk, random noise, and timing jitter, is developed to compare the three common modulation formats operating on electrical backplane channel models. In order to improve duobinary modulation efficiency, a low-power quarter-rate duobinary precoder circuit is proposed which provides significant timing margin improvement relative to full-rate precoders. Simulation results of the proposed transmitter in a 90 nm CMOS technology compare operation with the different modulation schemes over three backplane channels with different loss profiles.     

Low-jitter digital timing recovery techniques for CAP-based VDSL applications

In this paper, a digital timing recovery technique for carrierless amplitude and phase modulation (CAP)-based very-high-speed digital subscriber line (VDSL) applications is presented. A digital spectral line method is proposed for the timing tone extraction. It avoids the bandwidth expansion normally caused by the nonlinear property of the timing tone extraction block, and lowers the required sampling clock frequency. Also, an adaptive loop gain control scheme is proposed to reduce the timing jitter, simultaneously achieving both fast locking and low steady-state jitter. A prototype timing recovery circuit in a 0.35-/spl mu/m CMOS technology achieves 12.02-ps and 86-ps rms and peak-to-peak jitter, respectively, at 40-MHz operation. This is equivalent to about 0.1% of the symbol rate, and suitable for VDSL applications. The prototype IC consumes about 55 mW with a 3.0-V power supply.     

时钟抖动对射频脉宽调制性能的影响分析

在全数字发信机系统中,射频脉宽调制(RF-PWM)将基带调制信号的幅度与相位信息编码为输出脉冲的宽度和位置。由于数字信号处理器件的非理想特性,其时钟信号的上升沿和下降沿存在抖动误差,影响RF-PWM的输出信号质量。基于3种RF-PWM实现方案,本文通过公式推导确定了时钟抖动引入的非线性失真项,并给出了时钟抖动影响下不同方案输出脉冲信号底噪的数学解析式。最后利用Matlab软件,对不同方案在时钟抖动条件下的基波、奇次谐波和底噪进行仿真验证,结果证明理论推导正确;同时对信号的矢量幅度误差(EVM)和邻信道功率比(ACPR)进行仿真,分析出时钟抖动对信号带内外性能的影响。结果表明,时钟抖动引入的非线性失真主要体现为底噪的抬高;不同RF-PWM实现方案时钟抖动的影响特性各有不同,其中五电平方案对时钟抖动影响具有抑制效果,且随时间分辨力的增大而增大。     

Equalization and pre-emphasis based LVDS transceiver

This work presents an area-efficient, low-power, high data rate low voltage differential signal (LVDS) transmitter and receiver with signal quality enhancing techniques. The proposed common mode feedback scheme significantly reduces the size of the LVDS transmitter by eliminating the use of area consuming passive resistor and capacitor used for close loop stability compensation. A preemphasis technique has been introduced to enhance the transmitter output’s signal quality without significantly increasing the power draw. On the receiver part, an equalization technique has also been introduced to further enhance signal quality, increases data rate and improved jitter with relatively low power consumption. The LVDS transmitter consumes 5.4 mA of current while driving an external 100 ohm resistor with an output voltage swing of 440 mV. The chip consumes an area of 0.044 mm². This LVDS receiver has an input common mode range from 0.1 to 1.6 V. It consumes 34 mW of power with a maximum data rate of 2 Gbps. It consumes an area of 0.147 mm² a jitter of 11.74 ps rms. A test chip is implemented using 0.18 μm CMOS process.     

Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals

Testing of signal integrity (SI) in current high-speed ICs, requires automatic test equipment test resources at the multigigahertz range, normally not available. Furthermore, for most internal nets of state-of-the-art ICs, external speed testing is not possible for the newest technologies. In this paper, on-chip testing for SI faults in digital interconnect signals, using built-in high speed monitors, is proposed. A coherent sampling scheme is used to capture the signal information. Two monitors to test SI violations are proposed: one for undershoots at the high logic level and the other for overshoots at the low logic level. The monitors are capable of detecting small noise pulses and have been extended to test sequentially more than one signal. The cost of the proposed strategy is analyzed in terms of area, delay penalization, and test time. The effects of clock jitter and process variations are analyzed. Experimental results obtained in designed and fabricated circuits show the feasibility of the proposed testing strategy. A good agreement appears between the theoretical analysis, simulation results, and the experimental measurements.      

一种定时脉冲低抖动传输方案设计

针对时统系统中脉冲传输问题,提出了一种定时脉冲低抖动传输方案。介绍了定时脉冲低抖动传输系统的方案设计,对数字内插、锁相环、调制解调方案和相位模糊检测等关键技术进行了阐述,最后给出了定时脉冲低抖动传输系统设计实现方案及性能测试结果分析,利用示波器观察时统系统中脉冲传输抖动控制在4 ns以内,通过实际工程证明了其有效性。     

Adjacent-Channel and Quadrature-Channel Interference in Minimum Shift Keying

In this paper we present formulas for the computation of error probability in the presence of quadrature-channel or adjacentchannel interference in addition to intersymbol interference in a minimum shift keying system. The filters in the receiver and transmitter are arbitrary but with a finite number of poles. The effect of phase jitter in the main channel, phase and symbol timing misalignment in the interfering channels, and sampling time jitter is taken into account. The probability of error is averaged over the phase and symbol timing misalignment. Numerical results are presented for Butterworth filters in the receiver and transmitter with two, three, and four poles. Curves of error probability as a function of various variables (signal-to-noise ratio, bandwidth of receiver and transmitter filters, number of poles, channel frequency separation, phase jitter, sampling time, and symbol timing and phase misalignment) are presented. The method of this paper can readily be applied to other filters; hence, it can be used in the design and prediction of the performance of digital communication systems.     

高斯脉冲的超宽带系统抗时间抖动性能分析

由于收发信机之间的不同步、定时追踪及收发间的相对速率等因素所引起的时间抖动在超宽带通信中是不可避免的.详细推导出在单链路及多用户环境中时间抖动对高斯脉冲的跳时脉位调制超宽带系统的性能影响的数学表达式,并作了相应的仿真分析.结果表明,系统的抗时间抖动性能主要取决于单脉冲信号的自相关特性及引入时间抖动的严重程度.     

TD-LTE/TD-SCDMA多频多模终端射频一致性测试方案研究

本文根据3GPP TS36.521-1和TS 34.122标准,提出了一套支持TD-LTE和TD-SCDMA多频多模终端射频一致性测试方案。重点阐述了本方案中关于终端发射机、接收机的测试方法,并且分析了仪表和器件选型的原则,提出了一种适用于TD-LTE/TD-SCDMA多频多模终端射频一致性测试系统的射频接口箱的设计原理。     

一种用于14位250 MS/s ADC的3.5 Gb/s发送器

提出了一种用于14位250 MS/s ADC的数据发送器。该发送器输出采用电流模驱动方式,最高数据传输速率达3.5 Gb/s,数据输出仅需要2个数据端口。电路采用180 nm 1.8 V 1P5M CMOS工艺实现。测试结果表明,该发送器在3.5 Gb/s速率下的输出信号摆幅为800 mV,抖动峰峰值为100 ps,功耗为32 mW。采用该3.5 Gb/s数据发送器的ADC在250 MHz采样率下得到的信噪比为71.1 dBFS,无杂散动态范围为77.6 dB。     

A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver

A 2.5-GHz built-in jitter measurement (BIJM) system is adopted to measure the clock jitter on a transmitter and receiver. The proposed Vernier caliper and autofocus approaches reduce the area cost of delay cells by 48.78% relative to pure Vernier delay line structure with a wide measurement range. The counter circuit occupies an area of 19 $mu$ m $times$ 61 $mu$ m in the traditional stepping scan approach. The proposed equivalent-signal sampling technique removes the input jitter transfer path from the sampling clock. The power supply rejection design is incorporated into the delay cell and the judge circuit. The layout implementation, calibration, and test time of the proposed BIJM system are all improved. The core circuit occupies an area of only 0.5 mm $times$ 0.15 mm with the 90-nm CMOS process. The Gaussian and uniform distributions jitter is verified at a 5-ps timing resolution and a 2.5-GHz input clock frequency .      

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

By using the data timing control at the transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 3-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 $mu{hbox {m}}$ CMOS process. The measurement shows that the proposed TX reduces the RX jitters by about 30 ps (more than 50% of the added jitter due to CIJ and ISI) at the data rates from 2.6 Gb/s to 4.0 Gb/s. The proposed scheme can be applied to more than three parallel microstrip lines.      

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.      

A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.     

Timing jitter due to carrier linewidth of laser-diode pulse sourcesin ultra-high speed soliton transmission

We theoretically analyze the timing jitter due to both the carrier phase noise of laser-diode (LD) pulse sources and the Gordon-Haus effect in soliton transmission. A formula is derived for the timing jitter in terms of the carrier linewidth, one of the measurable parameters common to all types of LD pulse sources. The transmission distance restricted by the timing jitter is analyzed, and the carrier linewidths required for ultra-long distance and ultra-high speed soliton transmission are estimated as well. Recirculating loop experiments at 10 Gb/s are demonstrated using two pulse sources; a gain-switched DFB-LD and a sinusoidally driven monolithically integrated MQW-DFB-LD/MQW-EA modulator, which have different carrier linewidths due to their different pulse formation processes. The difference in the carrier linewidths of the two pulse sources is measured by the proposed technique which is based on the optical heterodyne method. The observed difference between the two pulse sources in terms of timing jitter accumulation and timing jitter reduction with optical bandpass filters for the two pulse sources well support the theoretical predictions     

具有滑频滤波器的光孤子通信系统时间抖动的研究

本文通过微扰理论，对采用滑频滤波器控制的孤子系统的时间抖动进行了研究。结果表明，滑频滤波器的引入，导致幅度和频率、幅度和滑频滤波器三阶项间的耦合，使得孤子传输系统的时间抖动增大，影响系统的传输极限。研究了滑频滤波器三阶项对滑频速率的影响，讨论和比较了具有滑频滤波器、固定频率滤波器和不加任何控制时的系统对由放大器的ＡＳＥ噪声产生的时间抖动的抑制结果。采用滑频滤波器是一种较好地抑制时间抖动的方法。     

The effect of timing jitter on the performance of a discretemultitone system

The transmission of high-speed data over severely band-limited channels may be accomplished through the use of discrete multitone (DMT) modulation, a modulation technique that has been proposed for a number of new applications. While the performance of a DMT system has been analyzed by a number of authors, these analyses ignore the effect of timing jitter on system performance. Timing jitter becomes an increasingly important concern as higher data rates are supported and larger constellations are allowed on the DMT subchannels. Hence, in this paper, we assume that synchronization is maintained by using a digital phase-locked loop to track a pilot carrier, Given this model, we derive error rate expressions for an uncoded DMT system operating in the presence of timing jitter, and we derive an expression for the interchannel distortion that results from a varying timing offset across the DMT symbol. In addition, we investigate the performance of trellis-coded DMT modulation in the presence of timing jitter. Practical examples from the asymmetric digital subscriber line (ADSL) service are used to illustrate various results     

RF interconnect for multi-gbit/s board-level clock distribution

With clock distribution of over 1 GHz, problems associated with clock skew, power consumption, and timing jitter are becoming critical for determining the processing speed of high-performance digital systems, especially for multi-processor systems. Conventional digital clock distribution interconnection has a severe power consumption problem for GHz clock distribution because of the transmission line losses, as well as exhibiting difficult signal integrity problems due to clock skew, clerk jitter and signal reflection. To overcome conventional digital clock distribution limitations, optical clock distribution techniques, based on guided-wave optics and free-space optics, have been proposed. However, the optical clock distribution is found to be bulky, hard to fabricate, and expensive, even though it has lower power consumption and excellent signal integrity properties. In this paper, a multi-Gbit/s clock distribution scheme to minimize power consumption, skew, and jitter, based on RF interconnect technology, especially for the medium clock frequency region from 200 MHz to 10 GHz, and interconnection line lengths of from 10 cm to 3 m, is proposed. A quantitative comparison is made between the guided optical, the free-space optical, the conventional digital, and the proposed RF interconnections for board-level clock distribution relative to power consumption and speed. The proposed board-level clock distribution with 32-fan-outs has successfully demonstrated less than 22-ps skew and less than 3-ps jitter at 2 GHz. The estimated power consumption of the clock link for the proposed clock distribution has been shown to be about 320 mW. Furthermore, the proposed clock receiver using the RF clock distribution scheme has demonstrated less than 2-ps dead time and 3-ps skew time